Fatima I. Sultan; Amna A. Slman; Uday M. Nayef
Abstract
Porous silicon (PS) layers has been prepared in this work by electrochemical etching (ECE) technique of a p-type silicon wafer with resistivity (1.5-4 Ω.cm) in hydrofluoric (HF) ...
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Porous silicon (PS) layers has been prepared in this work by electrochemical etching (ECE) technique of a p-type silicon wafer with resistivity (1.5-4 Ω.cm) in hydrofluoric (HF) acid of 20% concentration. Various affecting studied etching time (10, 30, and 45 min) and current density (15 mA/cm2). We have study the morphological properties (AFM) and the electrical properties (I-V and C-V). The atomic force microscopy investigation shows the rough silicon surface, with increasing etching process (etching time) porous structure nucleates which leads to an increase in the depth and width (diameter) of surface pits. Consequently, the surface roughness also increases. The electrical properties of prepared PS; namely current density-voltage characteristics under dark, show that the pass current through the PS layer decreased by increasing the etching time, due to increase the resistivity of PS layer. The PS layer shows a rectifying behaviour with different rectification ratio. C-V measurements shows that the increase of the etching time decreases the capacitance of the PS layer. This behavior was attributed to the increasing in the depletion region width which leading to the increasing of built-in potential.
