Print ISSN: 1681-6900

Online ISSN: 2412-0758

Keywords : SDR


Design and Implementation of Discrete Multitone Modulator for Digital Subscriber Line Using FPGA

Hadi T. Ziboon; Ikhlas M. Farhan

Engineering and Technology Journal, 2014, Volume 32, Issue 7, Pages 1797-1810

This paper presents a design, simulation and implementation of the Discrete Multitone (DMT) modulator for digital subscriber line (DSL) for both complex and real transmission based on Software Defined Radio (SDR) using FPGA. DMT divides the available bandwidth into parallel sub-channels. There are two techniques to transmit data by DMT. Complex transmission and real transmission .Real transmission is preferred for DSL, since it needs single wire but uses twice number of IFFT. The Simulink HDL Coder has been used for converting the MATLAB-Simulink and M-files models to VHDL language. The verification of the generated VHDL code has been done using Altera- ModelSim, while the synthesis reports and board programming files have been obtained using the Quartus II. The FPGA is used as a platform for SDR. The implementation by using Simulink HDL coder shows the feasibility and flexibility in solving the problems of implementation of the main units of DMT for both complex and real transmission. The main units of DMT are serial to parallel converter,MQAM,IFFT,Parallel to serial and cyclic prefix. The experimental results show that there is coincidence between generated real and complex signal and simulated real and complex signal by generated MATLAB (Simulink and M-file) and Simulink HDL Coder.

Design and Implementation of Programmable Multi-Mode Digital Modulator for SDR Using FPGA

Majid S. Naghmash

Engineering and Technology Journal, 2014, Volume 32, Issue 7, Pages 1655-1670

The design of programmable multi-mode digital modulator for software defined radio (SDR) technology using FPGA is developed and investigated in this paper. The system generator from Xilinx and MATLAB tools are used for FPGA design as well as the implementation of the modulator over a Virtex-4 FPGA board. The HDL language on Xilinx ISE is used to generate the bit stream of the modulator algorithms into ADC/DAC device and FPGA board. The modulated signal obtained from MATLAB simulation is evaluated with the tested signal to verify the system functionality. Lastly, the optimally synthesized netlist of the integrated design is downloaded into Xilinx Virtex-4 FPGA MB development board. The verification of DAC output signal via oscilloscope demonstrate the empirical real-time signals similar to the simulated waveforms. Results shows the successfully implementation steps as timing constraint of FPGA is accepted without error. The proposed design is promising to enhance the current and next generation of communication systems with less power consumption compared with conventional design in term of FPGA Slices and Look Up Tables (LUTs) during the implementation process. The improvement in Slices and LUTs produce by ISE project utilization summary is 65% and 79% respectively.

Design and Implementation of Adaptive Modulation Modem Based on Software Defined Radio(SDR) for WiMAX System

H. T. Ziboon; Zeinah Tariq Naif

Engineering and Technology Journal, 2010, Volume 28, Issue 14, Pages 4730-4749

This paper presents design and implementation of adaptive
modulation modem for WiMAX system. (BPSK, QPSK, 8QAM, 16QAM,
32QAM and 64QAM) are used in this work. Software Defined Radio(SDR)
is used for implementing this modem. This work examines the benefits of
using adaptive modulation in terms of probability of bit error and spectral
efficiency. It specifically examines the performance enhancement made
possible by using linear prediction along with channel estimation in
conjunction with adaptive modulation. Simulation results proved that the
adaptive system performance with estimator and predictor is better than
other modulation alone. The simulation results for adaptive modulation in
compared to each modulation technique alone show that for BER=10-3 with
(fd=50Hz -200Hz)system the improvement occurs by decreasing S/N by 2-
3dB. As for BER=10-4 with same Doppler frequency, the system
improvement takes place by decreasing S/N by 1.3dB- 4dB. Recarding
BER=10-5 with same Doppler frequency, the improvement is by decreasing
S/N by 1.5dB-5 dB. Simulation results also show the flexibility of the
adaptive system to operate with different level of modulation based on
switching of S/N. Matlab7.8(R2009a) used for simulation of adaptive
modulation system with AWGN and fading channel.

Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software Defined Radio

A. A. Thabit; H. T. Ziboon

Engineering and Technology Journal, 2009, Volume 27, Issue 10, Pages 2008-2026

This paper presents a design and simulation of digital PLL synchronizer, using
Costas loop based on SDR for high frequency communication systems. Design
parameters are selected for each unit of the proposed systems in order to
accommodate SDR requirements. Different techniques for carrier recovery based
on SDR are discussed. PLL techniques is chosen for synchronization, since it is
one of the most active synchronization techniques. BPSK and QPSK
synchronizers for coherent receivers have been designed and simulated based on
SDR using both Costas loop and modified Costas loop. The simulation result
shows that these two systems are reliable in recovering the carrier phase and
frequency when significant frequency and phase are present. Simulation result
shows that the BPSK system has Pe =10-3 at Eb / No equal to 8.5 dB in the
presence of AWGN and has the ability to track frequency offset up to 1200Hz
with 2*10 -4 probability of bit error at Eb / No equal to 20 dB. This system can
track phase offset 45 o with Pe =10-4 at Eb / No equal to 20 dB. For QPSK system,
the probability of bit error 10-3 at Eb / No =9dBand has the ability to track
frequency offset 300 Hz and phase offset=9 o with Pe =10-3 at Eb / No equal to
20dB.