Jabber H.Majeed
Abstract
In this paper, an FPGA (Field-programmable gate array) model of digital single phase power factor optimizer has been built. The proposed optimizer is based on measuring the phase shift ...
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In this paper, an FPGA (Field-programmable gate array) model of digital single phase power factor optimizer has been built. The proposed optimizer is based on measuring the phase shift time between voltage and current waveforms. Therefore, it is required to reduce this time to make the voltage and current waves in phase as possible. Thus, the power factor will be in maximum value (closed to unity). The process of improving the power factor is carried out by connecting a set of capacitors in parallel with the load. The proposed power factor optimizer has been built using VHDL (Very high speed integrated circuit Hardware Description Language), simulated using Xilinx ISE 9.2i package and implemented using Spartan-3A XC3S700A FPGA kit. Implementation and Simulation behavioral model results show that the proposed optimizer satisfies the specified operational requirements and reflected impressive results when applied to different loads.
