Print ISSN: 1681-6900

Online ISSN: 2412-0758

Keywords : FPGA


FPGA Implementation of Modified Reconfigurable Adaptive Gain Scheduling Controller

Ali Wheed; Abbas H. Issa; Mohammed Y. Y.

Engineering and Technology Journal, 2021, Volume 39, Issue 7, Pages 1105-1116
DOI: 10.30684/etj.v39i7.1772

This article aims to put forward a modified type of adaptive gain scheduling that will be able to deal with the immeasurable and unpredictable variations of system variables by adapting its value at each time instance to follow any change in the input and overcome any disturbance applied to the system without the need to predetermine gains values. In addition, the inverse neural controller will precede the gain scheduling to eliminate the need for complex system linear zing and parameter estimation. Therefore, the problems of needing complex mathematics for system linearization and gains calculations have been solved. The performance of the presented controller was tested by comparing the step response of a DC-motor controlled via the proposed technique and the response of that motor when controlled by the inverse neural controller and PID controller. MATLAB/Simulink has been used for making the simulations and obtaining the results. In addition, the FPGA implementation of the proposed controller has been presented. The results showed a remarkable improvement in the transient response of the system for all of the rising time, delay time, settling time, peak overshoot, and steady-state error.

Study of Power System Load Flow Using FPGA and LabVIEW

Ahmed Y. Yaseen; Afaneen A. Abbood

Engineering and Technology Journal, 2020, Volume 38, Issue 5, Pages 690-697
DOI: 10.30684/etj.v38i5A.346

The capability to rapidly execute the power flow (PF) calculations permit engineers in assured with stay bigger assured within the dependability, protection, and economical operation of their system within the case of planned or unplanned instrumentality failures. The purpose of this work is to investigate the use of FPGA characteristics to speed up power flow computing time for the on-line monitoring system of a power system. The work comprises which is the development of the Power flow program using the Fast-decoupled method based on FPGA (Field Programmable Gate Array), and LABVIEW (graphical programming environment). The program delivered very satisfactory results to solve a 30-bus test system. These findings suggest that in general that differences between the proposed work and the conventional fast decoupled method are satisfactory. As for the execution time, because the FPGA uses parallel solutions, the performance of the proposed method is faster. Also, the engagement of the FPGA and the LabVIEW program presented an effective monitoring system for observing the power system.a

FPGA Design and Implementation of Data Covering Based on MD5 Algorithm

Thamir R. Saeed

Engineering and Technology Journal, 2016, Volume 34, Issue 14, Pages 2621-2630

The protection of information leads to protection of individual privacy for everyone. This protection is performed using encryption. Many types of encryption may be utilized while the simplest one is the covering of information. In this paper, three novel algorithms have been presented for covering the information and for increasing the security. The degree of these security algorithms depends on three keys; MD5 core code, MD5 iteration, and mode of data hashing. The strengths of this work are the simplicity of the design and taken a long time for attack recovering the hashing data. Where, the sequence length for our proposed algorithms related to the MD5 output sequence length will be increased from 100% for 8-bit core code to 256% for scenarios E and F, while 1024% for scenario G with processing time is 20 nsec and 60 nsec depend on the scenarios. While the bit rate of the information data in transmitted data stream bits are different from 64-to- 32 bits for each transmitted stream bits depending on the scenario that selected. In this context, the maximum expected throughput is 806.596 Mbps. The implementation of algorithm circuits is built by using Xilinx Spartan 3-xc3s1400a-4fg484.

Intelligent Monitoring for DC Motor Performance Based on FPGA

Bilal Z. Ahmed; Abbas H. Issa

Engineering and Technology Journal, 2016, Volume 34, Issue 13, Pages 2490-2499

This paper presents a fault monitoring of DC motors. A neural network is prepared to processes the inputs parameters “motor speed and current” collected from sensors and delivers condition states of the DC motors “good, fair or bad”. FPGA Spartan 3 kit board is used to implement the proposed monitoring network and the circuits are designed for data acquisition to makes an interface between motors analog collected data and FPGAs digitals inputs ports. The designed circuits are intended to gather analogs readings from the target motor and converting them into digitals to be compatibles with FPGAs inputs ports specifications. The neural networks which are designed based on backs propagation trainings are implemented using Xilinx Spartan-3A Starter FPGAs Kits boards.

High Level Implementation Methodologies of DSP Module using FPGA and System Generator

Majid S. Naghmash; Mousa K. Wali; Amar A. Abdulmajeed

Engineering and Technology Journal, 2016, Volume 34, Issue 2, Pages 295-306

This paper presents the high level implementation methodologies of Digital Signal Processing (DSP) module by using the Field Programmable Gate Array (FPGA) andintegrated software environments (ISE) with the System Generator programs. The shortest and efficient paths to design a Xilinx Vertix-4 FPGA using MATLAB, ModelSim, synplify Pro software tools is introduced. The floating point design in MATLAB has been moved to fixed point values using Xilinx DSP system generator software a model based approach associated with assistance software from Mathworks and Synplicity. The obtained result shows an important utilization in FPGAarea.

Design and Implementation of Discrete Multitone Modulator for Digital Subscriber Line Using FPGA

Hadi T. Ziboon; Ikhlas M. Farhan

Engineering and Technology Journal, 2014, Volume 32, Issue 7, Pages 1797-1810

This paper presents a design, simulation and implementation of the Discrete Multitone (DMT) modulator for digital subscriber line (DSL) for both complex and real transmission based on Software Defined Radio (SDR) using FPGA. DMT divides the available bandwidth into parallel sub-channels. There are two techniques to transmit data by DMT. Complex transmission and real transmission .Real transmission is preferred for DSL, since it needs single wire but uses twice number of IFFT. The Simulink HDL Coder has been used for converting the MATLAB-Simulink and M-files models to VHDL language. The verification of the generated VHDL code has been done using Altera- ModelSim, while the synthesis reports and board programming files have been obtained using the Quartus II. The FPGA is used as a platform for SDR. The implementation by using Simulink HDL coder shows the feasibility and flexibility in solving the problems of implementation of the main units of DMT for both complex and real transmission. The main units of DMT are serial to parallel converter,MQAM,IFFT,Parallel to serial and cyclic prefix. The experimental results show that there is coincidence between generated real and complex signal and simulated real and complex signal by generated MATLAB (Simulink and M-file) and Simulink HDL Coder.

Design and Implementation of Programmable Multi-Mode Digital Modulator for SDR Using FPGA

Majid S. Naghmash

Engineering and Technology Journal, 2014, Volume 32, Issue 7, Pages 1655-1670

The design of programmable multi-mode digital modulator for software defined radio (SDR) technology using FPGA is developed and investigated in this paper. The system generator from Xilinx and MATLAB tools are used for FPGA design as well as the implementation of the modulator over a Virtex-4 FPGA board. The HDL language on Xilinx ISE is used to generate the bit stream of the modulator algorithms into ADC/DAC device and FPGA board. The modulated signal obtained from MATLAB simulation is evaluated with the tested signal to verify the system functionality. Lastly, the optimally synthesized netlist of the integrated design is downloaded into Xilinx Virtex-4 FPGA MB development board. The verification of DAC output signal via oscilloscope demonstrate the empirical real-time signals similar to the simulated waveforms. Results shows the successfully implementation steps as timing constraint of FPGA is accepted without error. The proposed design is promising to enhance the current and next generation of communication systems with less power consumption compared with conventional design in term of FPGA Slices and Look Up Tables (LUTs) during the implementation process. The improvement in Slices and LUTs produce by ISE project utilization summary is 65% and 79% respectively.

Low Complexity Spectrum Sensing System for GFDM Cognitive Radio Signals

Hussain K. Chaiel

Engineering and Technology Journal, 2014, Volume 32, Issue 6, Pages 1506-1518

Cognitive radio is a promising technology that aims to use the transmission spectrum efficiently. Each cognitive transmission process consists typically of two phases. During the first phase, which is called sensing phase, cognitive system attempts to detect an available spectrum hole. While in the second phase, data transmission phase, the secondary user data is transmitted to the destination via detected hole. The throughput of the cognitive radio system is mainly depending on the ratio of the transmission time to the sensing time. To reduce the sensing time, this paper suggests a design of simple spectrum sensing system capable for detecting Generalized Frequency Division Multiplexing (GFDM) signals. The reduction in sensing time is based on using XilinixVirtix-6 Field Programmable Gate Array (FPGA) as a target device for implementation the proposed design, which operates at 600 MHz clock frequency. This work includes a discussion of more than one approach to reduce the arithmetic operations needed to implement a sensing system with 250 subcarriers. The simulation results show that the power consumption represents the main challenge of such implementation.

Implementation of Golay Complementary Code Sequences Generator Based on FPGA

Dhamyaa H. Mohammed

Engineering and Technology Journal, 2013, Volume 31, Issue 11, Pages 2157-2165

Golay sequences have some properties make it distinctive in the applications and results. However, for this distinction must select the code sequences carefully and accurately. Therefore, to satisfy these requirements, a creation algorithm must be easy, accurate and powerful. In this paper, an FPGA based, design and implementation of Golay complementary code sequence(GCCS) creation and then made autocorrelation between their pair codes to verify properties. The process time for proposed algorithm is less than that for all possible algorithm by (1/4 to 1/1024 for 4-bit to 16 bits respectively). Thus, the Search can be regarded as pioneers of the research application of this technique to the subject and got good results. The Implementation was based on 8-bit pair code and made by Xilinx-spartan-3A XC3S700AFPGA, with 50 MHz internal clock.

Design and Implementation of MC-CDMA Technique Using FPGA

il A. H. Hadi; Layla Hattim Abood

Engineering and Technology Journal, 2013, Volume 31, Issue 11, Pages 2085-2097

Multicarrier Code Division Multiple Access (MC-CDMA) is attractive technique for high speed wireless data transmission; it's a combination of Orthogonal Frequency Division Multiplexing (OFDM) and Code Division Multiple Access (CDMA). OFDM employs a number of orthogonal subcarriers, this increases the symbol duration while the CDMA technique provides high capacity over other conventional multiple access schemes. In this paper discusses implementation of base band MC-CDMA system using the FPGA technique, all modules are designed using VHDL programming language. The electronic functional performance of designed circuits is tested by simulations using VHDL programming language on XILINX ISE 9.2i. The proposed model is designed using (Fast Fourier Transform/ Inverse Fast Fourier Transform) and the spreading code used is the gold code, the implementation of the proposed model using Spartan-3A/3AN, XC3S700N-3FGG484 FPGA of Xilinx family.

A VHDL Model for Implementation of MD5 Hash Algorithm

Mohammed A. Noaman

Engineering and Technology Journal, 2013, Volume 31, Issue 6, Pages 1107-1116

With the increase of the amount of data and users in the information systems, the requirement of data integrity is needed to be improved as well, so the work has become necessary independently. One important element in the information system is a key of authentication schemes, which is used as a message authentication code (MAC). One technique to produce a MAC is based on using a hash function and is referred to as a HMAC.MD5 represents one efficient algorithms for hashing the data, then, the purpose of implementation and used this algorithm is to give them some privacy in the application. Where they become independent work accessories as much as possible, but what is necessary, such as RAM and the pulse generator. Therefore, we focus on the application of VHDL for implement and computing to MD5 for data integrity checking method and to ensure that the data of an information system is in a correct state. The implementation of MD5 algorithm by using Xilinx-spartan-3A XCS1400AFPGA, with 50 MHz internal clock is helping for satisfies the above requirements.

Digital Single Phase Power Factor Optimizer Based on FPGA

Jabber H.Majeed

Engineering and Technology Journal, 2012, Volume 30, Issue 19, Pages 3371-3383

In this paper, an FPGA (Field-programmable gate array) model of digital single
phase power factor optimizer has been built. The proposed optimizer is based on
measuring the phase shift time between voltage and current waveforms. Therefore,
it is required to reduce this time to make the voltage and current waves in phase as
possible. Thus, the power factor will be in maximum value (closed to unity). The
process of improving the power factor is carried out by connecting a set of
capacitors in parallel with the load. The proposed power factor optimizer has been
built using VHDL (Very high speed integrated circuit Hardware Description
Language), simulated using Xilinx ISE 9.2i package and implemented using
Spartan-3A XC3S700A FPGA kit. Implementation and Simulation behavioral
model results show that the proposed optimizer satisfies the specified operational
requirements and reflected impressive results when applied to different loads.

Implementing of Forward Link Channel CDMA2000-1x System by Using Simulink HDL Coder

Hadi T. Ziboon; Alaa Y. Eisa

Engineering and Technology Journal, 2012, Volume 30, Issue 14, Pages 2381-2400

This work is a proposed simulation for forward link channel of CDMA2000 -1x
system by using QPSK, 8QAM and 16QAM, and converting the proposed system
to VHDL language by using Simulink HDL Coder for implementing in FPGA
board.
The results of simulation for forward link channel of CDMA2000 system shows
improvement when using three levels of codes (LPNC, Walsh code and complex
coding) in the present of AWGN for QPSK modulation the system performance is
improved from (1.8 to 1.9) in dB for BER (Bit Error Rate) 10 to 10 and for
8QAM the system performance is improved at (2.9) in dB for BER 10 to 10
and for 16QAM the system performance is improved from (1 to 1.2) in dB for BER
10 to 10 . The results of simulation in the present of AWGN and Rayleigh
fading channel are improvement within (0.5) in dB for the different Doppler
Frequencies (5 - 230Hz).
The Simulink HDL Coder has been used for converting the MATLABSimulink
models to VHDL language. The verification of the generated VHDL
code has been done using Altera-ModelSim program, while the synthesis reports
and board programming files have been obtained using the Quartus II program.
System implementation has been done using FPGA technology with Altera
Cyclone II boards. The implementation of the forward link channel by using
Simulink HDL coder shows feasibility and flexibility in solving the problem of
complex multiplication of complex spreading code also the practical results were
closed to that obtained from ModelSim program.

An FPGA Based Vehicles Density Dependent Intelligent Traffic Light System

Najmah A. Habeeb

Engineering and Technology Journal, 2012, Volume 30, Issue 13, Pages 2186-2196

In this paper, a vehicles density dependent intelligent traffic light system based on
FPGA has been built. The intelligent traffic light system counts the number of
available vehicles in the sides of the traffic intersection via the sensors placed on
the ends of the road. Subsequently, it determines passage time required for each
side, depending on the density of existing vehicles in it, in order to pass the largest
number of vehicles in the intersection during a certain time. The proposed system
is built using VHDL, simulated using Xilinx ISE 9.2i package, and implemented
using Spartan-3A XC3S700A FPGA kit. Implementation and Simulation
behavioral model results show that proposed system fits the specified functional
requirements, and finds a solution to overcome the problem of traffic jam at
intersections.

Design Neural Wireless Sensor Network Using FPGA

Ban M. Khammas

Engineering and Technology Journal, 2012, Volume 30, Issue 9, Pages 1641-1661

Wireless sensor networks(WSN) are an exiting emerging technology that
scientists believe to become a part of every day life in the next few years. However, at this time many issues in wireless sensor networks remain unresolved. This paper studies the architecture of a neural wireless sensor network designed to identify technical condition of the base station of wireless sensor networks ,and this work presents an on-chip artificial neural networks(ANN) in a Field Programmable Gate Arrays (FPGA) system. In order to take maximum advantage of the distributed architecture of multiple NN systems is to providing a high degree of parallelism between NNs and, hence, a higher speed-up in relation to a sequential implementation. The goal of this work is to realize the hardware implementation of the base station of neural wireless sensor network using FPGAs to measure hamidi ty, temperature and light for the security system of an office

Tx/Rx: Generation and Correlation of aCostas Array FM CodeUsing FPGA Spatran-3 Technology

Thamir R. Saeed

Engineering and Technology Journal, 2012, Volume 30, Issue 8, Pages 1394-1404

This paper describes a real time generation and correlation of Costas array FM code
pulse compression using Field Programmable Gate Array (FPGA) for implementation,
which provides the flexibility, reconfigure ability and reprogram ability. This
implementation contains two parts, the first Part, to generate. Number of frequency
sequences, which can use as Costas, where, this part was built in transmitter side. The
second part of implementation contains three stages in the receiver side; range
determination, correlation and Doppler measurement to the replica of Tx-signal. The
tested work was taken for eight digits and two cases of frequency shift (1&2) with an
eight time shift for each one. This implementation was built by using VHDL editor for
Spartan-3 with IC XC3S200. The clock is 20nsec and can use less than that time.

Design and Implementation of A Fpga Based Software Defined Radio Using Simulink HDL Coder

Hikmat N. Abdullah; Hussein A. Hadi

Engineering and Technology Journal, 2010, Volume 28, Issue 23, Pages 6750-6768

This paper presents the design procedure and implementation results of a
proposed software defined radio (SDR) using Altera Cyclone II family board. The
implementation uses Matlab/SimulinkTM, Embedded MatlabTM blocks, and Cyclone II
development and educational board. The design is first implemented in
Matlab/SimulinkTM environment. It is then converted to VHDL level using Simulink
HDL coder. The design is synthesized and fitted with Quartus II 9.0 Web Edition®
software, and downloaded to Altera Cyclone II board. The results show that it is easy
to develop and understand the implementation of SDR using programmable logic
tools. The paper also presents an efficient design flow of the procedure followed to
obtain VHDL netlists that can be downloaded to FPGA boards