Power Optimization of Binary Multiplier Based on FPGA
Power Optimization of Binary Multiplier Based on FPGA

Fadi Nasser; Ivan A. Hashim

Volume 39, Issue 10 , October 2021, , Page 1492-1505

https://doi.org/10.30684/etj.v39i10.2156

Abstract
  In the VLSI circuits, power dissipation is a critical design parameter and it plays a vital role in the performance of different digital systems. The decrease in chip size along with ...  Read More ...