Hazim Salah Abdalsatar
Abstract
In this paper, a design and implementation of a digital down converter (DDC) filter for GSM, CDMA, WCDMA is presented. A powerful system design tool, Xilinx System Generator is adopted ...
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In this paper, a design and implementation of a digital down converter (DDC) filter for GSM, CDMA, WCDMA is presented. A powerful system design tool, Xilinx System Generator is adopted to simplify the design cycle and increase the productivity. The proposed DDC is composed of three stages of cascaded filters. The maximum operation speed of the Proposed DDC filter is 100MHz. The remaining sub-modules of the DDC, such as the FIR filter, is co-designed using MATLAB FDATool and ModelSim with a tradeoff between the receiving path of requirements, algorithm and hardware implementation complexity. The system has been successfully verified using the MATLAB module and ModelSim. The most important stage in the design is the HDL code generation for implementation phase and results verification.
