Print ISSN: 1681-6900

Online ISSN: 2412-0758

Keywords : VHDL


FPGA Design and Implementation of Data Covering Based on MD5 Algorithm

Thamir R. Saeed

Engineering and Technology Journal, 2016, Volume 34, Issue 14, Pages 2621-2630

The protection of information leads to protection of individual privacy for everyone. This protection is performed using encryption. Many types of encryption may be utilized while the simplest one is the covering of information. In this paper, three novel algorithms have been presented for covering the information and for increasing the security. The degree of these security algorithms depends on three keys; MD5 core code, MD5 iteration, and mode of data hashing. The strengths of this work are the simplicity of the design and taken a long time for attack recovering the hashing data. Where, the sequence length for our proposed algorithms related to the MD5 output sequence length will be increased from 100% for 8-bit core code to 256% for scenarios E and F, while 1024% for scenario G with processing time is 20 nsec and 60 nsec depend on the scenarios. While the bit rate of the information data in transmitted data stream bits are different from 64-to- 32 bits for each transmitted stream bits depending on the scenario that selected. In this context, the maximum expected throughput is 806.596 Mbps. The implementation of algorithm circuits is built by using Xilinx Spartan 3-xc3s1400a-4fg484.

Implementing of Forward Link Channel CDMA2000-1x System by Using Simulink HDL Coder

Hadi T. Ziboon; Alaa Y. Eisa

Engineering and Technology Journal, 2012, Volume 30, Issue 14, Pages 2381-2400

This work is a proposed simulation for forward link channel of CDMA2000 -1x
system by using QPSK, 8QAM and 16QAM, and converting the proposed system
to VHDL language by using Simulink HDL Coder for implementing in FPGA
board.
The results of simulation for forward link channel of CDMA2000 system shows
improvement when using three levels of codes (LPNC, Walsh code and complex
coding) in the present of AWGN for QPSK modulation the system performance is
improved from (1.8 to 1.9) in dB for BER (Bit Error Rate) 10 to 10 and for
8QAM the system performance is improved at (2.9) in dB for BER 10 to 10
and for 16QAM the system performance is improved from (1 to 1.2) in dB for BER
10 to 10 . The results of simulation in the present of AWGN and Rayleigh
fading channel are improvement within (0.5) in dB for the different Doppler
Frequencies (5 - 230Hz).
The Simulink HDL Coder has been used for converting the MATLABSimulink
models to VHDL language. The verification of the generated VHDL
code has been done using Altera-ModelSim program, while the synthesis reports
and board programming files have been obtained using the Quartus II program.
System implementation has been done using FPGA technology with Altera
Cyclone II boards. The implementation of the forward link channel by using
Simulink HDL coder shows feasibility and flexibility in solving the problem of
complex multiplication of complex spreading code also the practical results were
closed to that obtained from ModelSim program.

An FPGA Based Vehicles Density Dependent Intelligent Traffic Light System

Najmah A. Habeeb

Engineering and Technology Journal, 2012, Volume 30, Issue 13, Pages 2186-2196

In this paper, a vehicles density dependent intelligent traffic light system based on
FPGA has been built. The intelligent traffic light system counts the number of
available vehicles in the sides of the traffic intersection via the sensors placed on
the ends of the road. Subsequently, it determines passage time required for each
side, depending on the density of existing vehicles in it, in order to pass the largest
number of vehicles in the intersection during a certain time. The proposed system
is built using VHDL, simulated using Xilinx ISE 9.2i package, and implemented
using Spartan-3A XC3S700A FPGA kit. Implementation and Simulation
behavioral model results show that proposed system fits the specified functional
requirements, and finds a solution to overcome the problem of traffic jam at
intersections.

FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption

Ashwaq Talib Hashim; Yousra A. Mohammed; Ekhlas H. Karam

Engineering and Technology Journal, 2010, Volume 28, Issue 9, Pages 1707-1718

Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs)
are highly attractive options for hardware implementations of encryption algorithms
as they provide cryptographic algorithm agility, physical security, and potentially
much higher performance than software solutions , therefore this paper investigates a
hardware design to efficiently implement block ciphers in VHDL based on FPGA’s.
This hardware design is applied to the new secret-key block cipher called 128-bits
improved Blowfish is proposed which is an evolutionary improvement of 64-bits
Blowfish designed to meet the requirements of the Advanced Encryption Standard
(AES) to increase security and to improve performance. The proposed algorithm will
be used a variable key size up to 192 bytes. It is a Type-3 Feistel network iterated
simple function 16 times.
The resources used to implement the design just described are: the VHDL
hardware description language, an FPGA platform from Xilinx and the Xilinx
Synthesis Technology (XST) software synthesis tools that belong to ISE 9.2i package.
The device of choice is the XCV600-4fg680 belonging to the Virtex family of
devices.
In this paper, a pipeline and sequential methods are used to get a high
througput (2.893Gbps) and a low area hardware design respectively.

Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language

Waleed Fawwaz Shareef

Engineering and Technology Journal, 2010, Volume 28, Issue 7, Pages 1350-1360

The wide spread of devices that use image processing in its
functions, like cellular phone and digital cameras, increases the need for
specialized processors for these functions as a replacement for software
programs that consume more time and resources. This paper presents a
hardware description for discrete wavelet transform (DWT) module in
VHDL language. The design involves the forward DWT (fDWT) and its
inverse (iDWT) characterized by variable number of transformation levels,
ranging from one level to seven levels. Each one of these two modules is
designed as hierarchical scheme that uses one-dimensional processing
module twice to represent two-dimensional processing. The module can be
used repeatedly on the same image for multilevel processing. Three
versions of the design are presented (v64, v128 and v256), each one
adapted different image size. Synthesis process showed that the design
frequency is about 56MHz. The simulation process showed that the
maximum possible rounding error is about 0.012%. This resolution with the
variable number of processing level adapts this design to fit in many
applications. Finally, a comparison of the proposed design with other
related work is presented, considering performance and specifications.

Represent Different Types of Sliding Mode Controllers by VHDL

Mohammed H. Khudair; Ekhlas H. Karam; Yousra Abd Mohammed

Engineering and Technology Journal, 2009, Volume 27, Issue 12, Pages 2494-2516

This paper focus on represent and implementation the conventional sliding mode control (SMC), in addition to some types of the common enhancement SMC approaches using reconfigurable hardware technology based on Field Programmable Gate Arrays (FPGAs); this is because FPGAs are highly attractive options for hardware implementation. The enhancement SMC approaches that used here are:1) the conventional SMC with boundary layer, 2) PI sliding mode controller, and 3) boundary SMC with new approximation sign function. The main key of this work is to
implement these SMC approaches in high volume FPGA devices, a low area and fast clock speed device, where these approaches are implemented in Xilinx Vertix family Xcv1000-fg680-4 FPGA (the occupation rate is 86% and maximum net delay is 0.032 ns). All the architectures in VHDL, verified the functionality using Active-HDL simulator, and synthesis the data paths using ISE 4.1i software package synthesis tool
and Xilinx place and route tool of this package. Finally, to test the performances of the enhancement SMC approaches, computer simulation is performed on linear and nonlinear system models in order to compare the performance of these SMC approaches to illustrate which approach between them give more efficient performance than the others

Design and Implementation of Synthesizable VHDL Model for General PCMCIA I/O Cards Controller

Yousra Abd Mohammed

Engineering and Technology Journal, 2008, Volume 26, Issue 7, Pages 762-776

Abstract
The portable and nomadic computer market has driven the development of
PCMCIA Cards to address the expansion needs for the user. These cards provide a
vast variety of hardware devices which are rugged, credit-card sized, lightweight,
and power efficient. These cards are easy to use, especially for the non-technical
user. Since the sockets are accessible from the outside of the system, the system
does not have to be powered-off, opened, and rebooted to add or remove a device.
This dynamic insertion and removal feature inherently makes these devices power
manageable and also allows devices to easily be shared among different computers.
This paper is concerned with type II PC cards, which mean I/O cards,
therefore a design and implementation of synthesizable VHDL model for control
system (Controller) of the PCMCIA I/O cards is presented.
The implementation of the control system (controller) has been done by using very
high speed hardware descriptive language (VHDL) and its implementation on field
programming gate array (FPGA) type Xilinx Spartan 2 (XC2S30-6 Pq208) by
using synthesis and implement tools of ISE6.3 program.
The used of FPGA technology is optimal for this paper because it offers high
reliability and flexibility in modifying and even developing the required design
with a reduction in the required number of hardware components, also the non
recurring engineering cost.
The timing behavior of the controller is be tested and verified to ensure
that it meets the performance requirements by using simulation tools of Active-
HDL program AND Daley report of ISE program, therefore examples of
simulation results of read/write transfers for both an attribute memory and I/O
devices are presented in this paper.

Implementing Fuzzy Logic Controller Using VHDL

Yousra A. Mohammed; Leena K. Hashim

Engineering and Technology Journal, 2007, Volume 25, Issue 9, Pages 1049-1055

Design of a Fuzzy Logic Controller (FLC) requires more design decisions than
usual, for example rule base, inference engine, defuzzifiction, and data pre- and
post processing.
This paper describes a way to implement a simple (FLC) in VHDL, there are
three parts to fuzzy controller, the fuzzification of the inputs, the defuzzification
of the outputs, and the rule base. The controller that is implemented has
demonstrated a 2-input, 1-output fuzzy controller with 5-membership functions.
This paper identifies and describes the design choices related to simple fuzzy logic
controller, based on an international standard which is underway.
In this paper, we propose a VHDL-based logic synthesis approach for designing
to reduce design time. A complete description of the controller (A fuzzier,
defuzzifier parts and a rule based are written in VHDL by using Active_HDL and
are assembled and synthesized using logic synthesis tools of ISE4.1 software. The
efficiency of the generated hardware is explored for FPGAs technology.