Print ISSN: 1681-6900

Online ISSN: 2412-0758

Keywords : and FPGA

FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption

Ashwaq Talib Hashim; Yousra A. Mohammed; Ekhlas H. Karam

Engineering and Technology Journal, 2010, Volume 28, Issue 9, Pages 1707-1718
DOI: 10.30684/etj.28.9.1

Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs)
are highly attractive options for hardware implementations of encryption algorithms
as they provide cryptographic algorithm agility, physical security, and potentially
much higher performance than software solutions , therefore this paper investigates a
hardware design to efficiently implement block ciphers in VHDL based on FPGA’s.
This hardware design is applied to the new secret-key block cipher called 128-bits
improved Blowfish is proposed which is an evolutionary improvement of 64-bits
Blowfish designed to meet the requirements of the Advanced Encryption Standard
(AES) to increase security and to improve performance. The proposed algorithm will
be used a variable key size up to 192 bytes. It is a Type-3 Feistel network iterated
simple function 16 times.
The resources used to implement the design just described are: the VHDL
hardware description language, an FPGA platform from Xilinx and the Xilinx
Synthesis Technology (XST) software synthesis tools that belong to ISE 9.2i package.
The device of choice is the XCV600-4fg680 belonging to the Virtex family of
In this paper, a pipeline and sequential methods are used to get a high
througput (2.893Gbps) and a low area hardware design respectively.

Design and Implementation of Synthesizable VHDL Model for General PCMCIA I/O Cards Controller

Yousra Abd Mohammed

Engineering and Technology Journal, 2008, Volume 26, Issue 7, Pages 762-776

The portable and nomadic computer market has driven the development of
PCMCIA Cards to address the expansion needs for the user. These cards provide a
vast variety of hardware devices which are rugged, credit-card sized, lightweight,
and power efficient. These cards are easy to use, especially for the non-technical
user. Since the sockets are accessible from the outside of the system, the system
does not have to be powered-off, opened, and rebooted to add or remove a device.
This dynamic insertion and removal feature inherently makes these devices power
manageable and also allows devices to easily be shared among different computers.
This paper is concerned with type II PC cards, which mean I/O cards,
therefore a design and implementation of synthesizable VHDL model for control
system (Controller) of the PCMCIA I/O cards is presented.
The implementation of the control system (controller) has been done by using very
high speed hardware descriptive language (VHDL) and its implementation on field
programming gate array (FPGA) type Xilinx Spartan 2 (XC2S30-6 Pq208) by
using synthesis and implement tools of ISE6.3 program.
The used of FPGA technology is optimal for this paper because it offers high
reliability and flexibility in modifying and even developing the required design
with a reduction in the required number of hardware components, also the non
recurring engineering cost.
The timing behavior of the controller is be tested and verified to ensure
that it meets the performance requirements by using simulation tools of Active-
HDL program AND Daley report of ISE program, therefore examples of
simulation results of read/write transfers for both an attribute memory and I/O
devices are presented in this paper.

Implementing Fuzzy Logic Controller Using VHDL

Yousra A. Mohammed; Leena K. Hashim

Engineering and Technology Journal, 2007, Volume 25, Issue 9, Pages 1049-1055

Design of a Fuzzy Logic Controller (FLC) requires more design decisions than
usual, for example rule base, inference engine, defuzzifiction, and data pre- and
post processing.
This paper describes a way to implement a simple (FLC) in VHDL, there are
three parts to fuzzy controller, the fuzzification of the inputs, the defuzzification
of the outputs, and the rule base. The controller that is implemented has
demonstrated a 2-input, 1-output fuzzy controller with 5-membership functions.
This paper identifies and describes the design choices related to simple fuzzy logic
controller, based on an international standard which is underway.
In this paper, we propose a VHDL-based logic synthesis approach for designing
to reduce design time. A complete description of the controller (A fuzzier,
defuzzifier parts and a rule based are written in VHDL by using Active_HDL and
are assembled and synthesized using logic synthesis tools of ISE4.1 software. The
efficiency of the generated hardware is explored for FPGAs technology.