Print ISSN: 1681-6900

Online ISSN: 2412-0758

Keywords : Spartan

FPGA Design and Implementation of Data Covering Based on MD5 Algorithm

Thamir R. Saeed

Engineering and Technology Journal, 2016, Volume 34, Issue 14, Pages 2621-2630

The protection of information leads to protection of individual privacy for everyone. This protection is performed using encryption. Many types of encryption may be utilized while the simplest one is the covering of information. In this paper, three novel algorithms have been presented for covering the information and for increasing the security. The degree of these security algorithms depends on three keys; MD5 core code, MD5 iteration, and mode of data hashing. The strengths of this work are the simplicity of the design and taken a long time for attack recovering the hashing data. Where, the sequence length for our proposed algorithms related to the MD5 output sequence length will be increased from 100% for 8-bit core code to 256% for scenarios E and F, while 1024% for scenario G with processing time is 20 nsec and 60 nsec depend on the scenarios. While the bit rate of the information data in transmitted data stream bits are different from 64-to- 32 bits for each transmitted stream bits depending on the scenario that selected. In this context, the maximum expected throughput is 806.596 Mbps. The implementation of algorithm circuits is built by using Xilinx Spartan 3-xc3s1400a-4fg484.

Tx/Rx: Generation and Correlation of aCostas Array FM CodeUsing FPGA Spatran-3 Technology

Thamir R. Saeed

Engineering and Technology Journal, 2012, Volume 30, Issue 8, Pages 1394-1404

This paper describes a real time generation and correlation of Costas array FM code
pulse compression using Field Programmable Gate Array (FPGA) for implementation,
which provides the flexibility, reconfigure ability and reprogram ability. This
implementation contains two parts, the first Part, to generate. Number of frequency
sequences, which can use as Costas, where, this part was built in transmitter side. The
second part of implementation contains three stages in the receiver side; range
determination, correlation and Doppler measurement to the replica of Tx-signal. The
tested work was taken for eight digits and two cases of frequency shift (1&2) with an
eight time shift for each one. This implementation was built by using VHDL editor for
Spartan-3 with IC XC3S200. The clock is 20nsec and can use less than that time.