Print ISSN: 1681-6900

Online ISSN: 2412-0758

Keywords : VHDL design

An FPGA Based a Digital Circuit Design for Route Optimization

Ivan A. Hashim

Engineering and Technology Journal, 2012, Volume 30, Issue 7, Pages 1117-1131

Route optimization is searching problem to find the shortest path from starting to end point within certain criteria. In this paper, a digital circuit design implementation was presented according to the Dijkstra algorithms and with new digital technology. The proposed circuit is built using VHDL and simulated using Xilinx ISE 9.2i package. The test of the implemented circuit was made by use a 25 point network map
to select the shortest path between any two specific points (from point 3 to point 24). Simulation behavioral model results show that proposed circuit satisfies the specified operational requirements. The result appears this requirement with a short time (depend on the clock frequency used 50MHz). Furthermore, this circuit is flexible to
increase the number of point in the map network.

Tx/Rx: Generation and Correlation of aCostas Array FM CodeUsing FPGA Spatran-3 Technology

Thamir R. Saeed

Engineering and Technology Journal, 2012, Volume 30, Issue 8, Pages 1394-1404

This paper describes a real time generation and correlation of Costas array FM code
pulse compression using Field Programmable Gate Array (FPGA) for implementation,
which provides the flexibility, reconfigure ability and reprogram ability. This
implementation contains two parts, the first Part, to generate. Number of frequency
sequences, which can use as Costas, where, this part was built in transmitter side. The
second part of implementation contains three stages in the receiver side; range
determination, correlation and Doppler measurement to the replica of Tx-signal. The
tested work was taken for eight digits and two cases of frequency shift (1&2) with an
eight time shift for each one. This implementation was built by using VHDL editor for
Spartan-3 with IC XC3S200. The clock is 20nsec and can use less than that time.