Engineering and Technology Journal

The needs for increasing the power generation make the use of solar cells plays an important role in the daily life. For this reason, it is important to use solar tracking system to increase or getting almost optimum amount from solar cells. In this paper, proposed intelligent controllers were designed and used to make solar cells facing the sun over the year. The proposed controller was trained by two ways; the first was trained by supervised feed forward neural network and the second by Particle Swarm Optimization (PSO) the results obtained for both designs are then compared. The controller was trained using MATLAB and then converted to SIMULINK model in order to test it, and convert it to a Very high speed integrated circuit Hardware Description Language (VHDL) language using MATLAB tool box in order to download it on Spartan 3A Field Programmable Gate Arrays (FPGAs) card. This makes the implementation of the intelligent controller more efficient and easy to use because of its reprogram-ability and the high speed performance. The controller was designed to a fully controlled DC motor driver which is used to rotate two DC motors in X-axis and Y-axis directions respectively.
The experimental results show that tracking sun increases the efficiency of the system to produce energy from solar cell about 44.3778 % more energy than the solar cell without tracking system.

This paper proposes hybrid architecture of feedforward/feedback second order
single-loop modulator for high resolution analog-to-digital converter (ADC)
applications. Different techniques for oversampling modulator are discussed. The
proposed architecture consists of three stages. The first stage is 2nd order single
loop oversampling ADC with novel feedforward/feedback architecture. In the
second stage, an error cancellation circuit (ECC) is proposed at the output of the
modulator to noise shaping of quantization noise. In addition, the third stage is a
decimation filter in order to reduce the oversampling ratio (OSR) which is suitable
for broadband applications. With low OSR=24, the signal-to-noise ratio (SNR) is
improved about 55 dB if compared with traditional architecture (feedback singleloop
high order topology). The achieved resolution or the effective number of bits
(ENOB) is (22-bit). With high OSR=256, the net improvement in quantization
noise reduction is 64 dB if compared with feedforward architecture (single-loop
high order) and the ENOB=28. Finally a 1-bit quantizer is used in the proposed
architecture which greatly decreases the circuit implementation complexity and
power consumption. Simulation results show the superiority performance of
proposed hybrid architecture as compared with traditional modulator topologies
(feedforward and feedback).

In this paper, a unipolar single-slope integrating analog-to-digital
converter(ADC) is discussed, designed, and simulated, whereas, its conversion
time is less than that of the dual-slope integrating ADC.The proposed system
consists of logarithmic amplifier,anti-logarithmic amplifier, integrator, counter,
control logic unit and two timers stages.
The proposed design characterizes some of significant properties which
make it distinguished from the other previous designed systems, such as, it has
good noise immunity because of passing of the analog input signal through the
integrator circuit which it considered as a low pass filter. This system is capable
to convert an analog voltage of range of (0.0 – 0.6) volt using non-linear
amplifiers. At last, this system has very good forward linearity relation between the
output digital number and the analog input voltage value which is realized later by
theoretical calculation and simulation results.
This system is simulated and tested using software package Electronic
Workbench version V9, and one can see that simulation results approach to the
theoretical results, so for this reason, this system possesses acceptable design and
performance.