%0 Journal Article
%T Floating Point Optimization Using VHDL
%J Engineering and Technology Journal
%I University of Technology-Iraq
%Z 1681-6900
%A Hammadi Jassim, Manal
%D 2009
%\ 12/01/2009
%V 27
%N 16
%P 3023-3049
%! Floating Point Optimization Using VHDL
%R 10.30684/etj.27.16.11
%X Due to inherent limitations of the fixed-point representation, it is sometimes desirable to perform arithmetic operations in the floating-point format. Although an established standard for floating-point arithmetic exists, optimal hardware implementations of algorithms require use of floating-point formats different fromthe ones specified in the standard. Hardware modules for floating-point format control, arithmetic operators and conversion to and from any fixed-point format are presented. Synthesis results for arithmetic operator modules in several floating-point formats, including the IEEE single precision format, Synthesis and processing results for both implementations are shown and compared
%U https://etj.uotechnology.edu.iq/article_43863_e59482a5e611a343f65e5dfdd397441e.pdf