Design of RF Power Amplifiers using Parallel-Series Power Combining Transformers

This paper presents the design of a one watt-level RF CMOS Power Amplifier (PA) based on power combining transformers PSCT in 0.13 µm technology using ADS 2011.10. The PA incorporates a parallel combination of four differential PA cores to generate high output power with acceptable efficiency and linearity. The first part the design for class-AB PA for WLAN applications is presented. The PA delivers an Output Power (Pout) of 30 dBm, Power Gain (Gp) of 30 dB and 40% PAE using 2.5 V supply. In the second part a class-E PA is designed to provide an output power of 30 dBm, power gain of 30 dB, and 54% PAE at 2.45 GHz using 1.6 V supply. The layout of the transformers is designed and simulated with momentum RF EM simulator of ADS 2011.10 in order to realize a fully integrated power amplifier. The simulated efficiency of the designed transformer was 78% with minimum insertion losses ( ILmin ) of 0.87 dB.


INTRODUCTION
MOS has for a long time been a good choice for digital integrated circuits (IC) due to its low cost, high level of integration and constant enhancements in its performance. Due to the significant scaling of MOS transistors, the transition frequency has reached well beyond 100 GHz and CMOS technology have become popular in wireless applications. At high frequencies, the major difficulty for CMOS PA is to achieve high output power. This is because at high frequencies, CMOS has low DC bias voltage of only about 2 volts. This low DC bias voltage has two effects, first relatively low RF output power due to low DC input power for any reasonable value of DC input current, second the optimum impedance is proportional to ( ) ⁄ . Low DC supply voltage leads to low RF impedance, which is very difficult to match to 50 ohms load impedance without losses. Furthermore, silicon substrate is usually conductive, which results in substantial additional loss at RF frequencies.

Power Combining Techniques
Transform-type combiner can be categorized as Series-Combining Transformers (SCTs) and Parallel-Combining Transformers (PCTs) according to their ways of voltage and current combining at the load. The advantage of PCT configuration is a reduction of the secondary inductor losses due to a reduction of the current flowing through them but at the cost of a larger area and a lower self-resonant frequency. Moreover, the PCT requires higher turn ratios in order to get the same output impedance compared to a SCT, which increases the losses in practice. On the other hand, a combination of SCT and PCT topologies is also possible in order to combine the advantages of both transformer topologies in a Parallel-Series Combining Transformer (PSCT) topology [1].
The hybrid-type power combining transformer (PSCT) performs the parallel (or current) and the series (or voltage) combining simultaneously in a single structure enabling the implementation of the power combining transformer in a smaller form-factor compared to the SCT. Moreover, the mutual inductance at the primary side in the PSCT is increased due to additional coupling between adjacent primary inductors, leading to improved efficiency and PTR (Power Transmission Ratio). The PSCT topology and its equivalent circuit model are presented in Figure (1). The total combining inputs in the PSCT is M = * where , are the parallel and series combining parts respectively. the input impedance of the PSCT can be obtained by the following equations [1]:

Design of RF Power Amplifiers using Parallel-Series Power Combining Transformers
If the coupling effect and the frequency dependent inductor are ignored, the input impedance of the PSCT can be simplified as: The input impedance of the PSCT is negligibly affected by the number of combining inputs if the number of series and parallel combining parts are same. The efficiency and the optimal primary inductance value of the PSCT can be obtained by the following equations [1]:

...(4)
Where N represents the turn ratio of the transformer, K is the coupling factor, and Q is the quality factor.

Design of a Watt-Level Class AB Power Amplifier for WLAN Applications
In Class AB, the conduction angle is between 180• and 360•, the DC bias voltage of the gate-to-source ( ) is slightly above the threshold voltage ( ) and the transistor is biased at a small drain current. As the name suggests, class-AB is the intermediate class between class-A and class-B. A single-ended class-AB power amplifier topology is shown in Figure (2). For a 0.13 µm CMOS, 1.2 V and 2.5 V are available. Using

Design of RF Power Amplifiers using Parallel-Series Power Combining Transformers
Equation (5)  ... (6) Equation (6) gives the optimum load to be presented at the PA outout, Under 1.2 V and 2.5 V for an output power 125 mW are 6 Ω and 25 Ω respectively. It is clear that 1.2 V is not sufficient because impedance transformation between 6 Ω and 50 Ω is too hard to be realized in practice. So, 2.5 V is a good choice for the design. The LC tank circuit ( , ) is designed to resonate at and block higher harmonics from proceeding towards the load, so that [3]: Where is the load quality factor and is selected to be 15. Using the load pull simulation , the value of the optimum load impedance obtained from the simulation ( = 13.132 + 3.026) at which the individual PA can deliver 25.6 dBm with maximum PAE.

Figure (2): Schematic of a single stage class _AB power amplifier. Class -AB Power Amplifier Design Based on PSCT
The PA is a four stages, all transformer-coupled design, the turn ratio of the transformer can be determined using Equation (4)

Design of a Watt Level Class-E Power Amplifier using Power-Combining Transformers
A single-ended class-E amplifier with shunt capacitor topology is shown in Figure  (7). The component values of the single ended class E PA are calculated at output power 125 mW (≈ 21 dBm), operating frequency 2.45 GHz. In 0.13 µm CMOS technology drain supply voltage of 1.2 V and 2.5 V are available, both values will provide an impedance transformation ratio that is too hard to be realized in practice for the PA design based on PSCT. Therefore the supply voltage is chosen to be 1.6 V. The components values are determined using the following equations [10]: R s is usually called optimum load resistance (R opt ) designed according to the specification on output power and the supply voltage. The series tank, consisting of and , is inserted to suppress higher harmonic content in the load.. L RFC can be calculated by the resonant equation of an LC tank [8]: ... (15) where C 1 is the cancelation capacitance by the inductor, C p is the MOSFET output capacitance and C s is the capacitance of the class_E PA. LC tank is the most simple and straight forward matching network that has been widely used in all kinds of PAs, however. A single-stage LC tank matching network basically has a forms as shown in Figure (8). The values of L m , C m , and can be calculated using the following equations [9]: ...

Class-E Power Amplifier Design Based on PSCT
The designed PA incorporates four stages differential stages with each stage delivers 250 mW approximately based on PSCT power combining. The topology of differential PA is shown in Figure(9).The schematic and the performance of the designed PA based on PSCT as a function of the input power are shown in Figure (10) and (11) respectively, it delivers an output power of 30 dBm with PAE of 54% at input power 0 dBm. In order to estimate the linearity of the PA, the 1-dB gain compression simulation is performed, the simulation result is shown in Figure (12). The power amplifier reaches its output 1-dB compression at 30 dBm, with an input power level of 1 dBm. The simulated performance of the PA as a function of frequency for an input power of 0 dBm is shown in Figure (13). As shown from this figure, the output power of the PA remains almost flat over the band, which is from 2.4 GHz to 2.48 GHz. The minimum PAE is 51.6 % . The performance of the designed PA is compared with other state-of-the-art linear CMOS PAs as illustrated in Table (2).

EM-Simulation of the Proposed Transformer
The power combining transformer PSCT is implemented with four primary inductors i.e. four power amplifier stages. The PSCT is composed of a series combining

Design of RF Power Amplifiers using Parallel-Series Power Combining Transformers
of two PCTs that have two primary inductors interwoven to the secondary inductor. Thus, the transformer exhibits a series-combining of two parallel-combining parts (i.e., = 2, = 2) with the total combining inputs of M = 4 .The turn ratio of the PCT is ( ×1: n) is used fixed to ensure that ( = ).The transformer was implemented using two thick metals (4µm-thick aluminum and 3µm-thick copper) that are connected through whole via trace as shown in Figure (14). The width of the inductor metal traces (30 µm) was chosen. The EM simulation shows that each primary inductor and the secondary inductor have the self inductance of 0.8 nH and 3.8 nH with quality factor the of 11.6 and 9 at 2.45 GHz, respectively, the size of the PSCT layout is 1.36×0.52 2 . The quality factor (Q) can be expressed by the ratio between the imaginary and real part of the input impedance [14]: The inductance can be extracted from the input resistance:      Conclusion A hybrid-type (parallel-series) power-combining transformer was designed to implement a fully-integrated watt level CMOS PA. The designed PA incorporates four stages differential PA based on PSCT. Linear PA class_AB designed for WLAN applications, it delivers an output power of 30 dBm with PAE of 40% using 2.5 V supply voltage. Nonlinear PA class_E designed to deliver an output power of 30 dBm with PAE of 54% using 1.6 V supply voltage.