State Space Parallelization Method for a 16-Bit Turbo Encoder
Engineering and Technology Journal,
2019, Volume 37, Issue 12A, Pages 553-557
AbstractTurbo codes are widely used in digital communication systems. Their ability to reach the Shannon channel capacity made it the choice for most of the communication systems. Due to the huge amount of the transmitted data, there is a need to increase the processing speed of the encoders. The researchers used the state space technique to enhance the throughput of the turbo encoder. They apply it to increase the turbo encoder throughput from one bit per cycle up to 8 bit per cycle. The researchers applied the state space method to a three-flip flop, eight state Recursive Systematic Convolution Code circuit to achieve their goal. In this paper, we explored the state space technique and applied it to a four flip-flop Recursive Systematic Convolution Code circuit so that we can achieve a throughput of 16 bit per cycle. The circuit was designed and tested using MATLAB then implemented using FPGA to verify its operation.
 H. Robert and M. Zaragoza, “The art of error
correcting,” A John Wiley & Sons, 2002.
 C. Berrou and A. Glavieux, “Near optimum error
correcting coding and decoding: turbo-codes,” IEEE
transaction on communications, vol. 44, no. 10, pp. 1261–
 T. K. Moon, “Error Correction Coding: Mathematical
Methods and Algorithms,” A John Wiley & Sons, 2005.
 H. Chuang, K. Tseng, and W. Fang, “A HighThroughput Radix-4 Log-MAP Decoder With Low
Complexity LLR Architecture,” IEEE Journal of SolidState Circuits, vol. 1, no.1, pp.231–234, 2009.
 C. Studer, C. Benkeser, S. Belfanti, and Q. Huang,
“Design and implementation of a parallel turbo-decoder
ASIC for 3GPP-LTE,” IEEE Journal of Solid-State
Circuits, vol. 46, no. 1, pp. 8–17, 2011.
 A. A. Purwita, A. Setio, and T. Adiono, “Optimized 8-
Level Turbo Encoder Algorithm and VLSI Architecture
for LTE,” International Conference on Electrical
Engineering and Informatics, July 2011.
 M. Ayinala and K. K. Parhi, “High-Speed Parallel
Architectures for Linear feedback Shift Registers,” IEEE
Transaction on signal processing, vol. 59, no. 9, pp. 4459–
 M. Ayinala and K. K. Parhi, “Efficient parallel VLSI
architecture for linear feedback shift registers,” Signal
Process. Syst. (SIPS), 2010 IEEE Work, pp. 52–57, 2010.
 Q. Al-doori and O. Alani, “A Multi Polynomial CRC
Circuit for LTE-Advanced Communication Standard,” 7th
Computer Science and Electronic Engineering Conference
(CEEC), pp. 19–23, 2015.
 J. H. Derby, “High-Speed CRC Computation Using
Stat-Space Transformations,” Global Telecommun. Conf.
(GLOBECOM’01) .IEEE, vol. 1, pp. 166–170, 2001.
 M. Grymel and S. B. Furber, “A novel programmable
parallel CRC circuit,” IEEE Trans. Very Large Scale
Integr. Syst., vol. 19, no. 10, pp. 1898–1902, 2011.
 D. J. C. MacKay, “Information theory, inference, and
learning algorithms,” Cambridge University, Version 7.2
(fourth printing) March 28, 2005.
 “Multiplexing and channel coding,” 3GPP TS 36.212
version 8.4.0, September 2008.
 S. Kumar and H. Dalal, “Performance comparision of
turbo codes and modified turbo codes,” International
Journal of Science, Eng and Technology Research
(IJSETR), vol. 3, no. 5, pp. 1520–1523, 2014.
 A. Imran, “Software implementation and performance
of UMTS turbo decoder,” MSc. thesis, Tampere Univ of
 C. Benkeser, A. Burg, T. Cupaiuolo, and Q. Huang,
“Design and optimization of an HSDPA turbo decoder
ASIC,” IEEE Journal of Solid-State Circuits ,vol. 44, no. 1,
pp. 98–106, 2009.
 H.Ljunger,”Turbo decoder with early stopping
criteria,” MSc. thesis, Lund Univ 2016.
 M.Ayinala and K. K. Parhi, “Efficient parallel
architecture for linear feedback shift registers,” IEEE
Transaction on signal processing, vol. 62, no. 11, pp.
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