Power Optimization of Binary Multiplier Based on FPGA
Engineering and Technology Journal,
2021, Volume 39, Issue 10, Pages 1492-1505
AbstractIn the VLSI circuits, power dissipation is a critical design parameter and it plays a vital role in the performance of different digital systems. The decrease in chip size along with the increase in chip density and complexity will increase the difficulty in designing higher performance and low power digital systems. Therefore, achieving a fast and low power system is the major concern of VLSI designers. Most of the digital systems have different math operations in their architectures. This paper focuses on the multiplication operation. Multiplication requires more iterations, long time, large area, and consumes high power of the digital system compared with the other basic computation operations. Hence to improve the system's performance, it is required to design a high speed and low power multiplier. In this paper, a dynamic power dissipation is targeted; therefore, different designs of multiplier algorithms such as a sequential multiplier, array multiplier, Booth’s multiplier (Radix-2), and modified Booth’s multiplier (Radix-4) are proposed to investigate the design that consumes the lowest dynamic power. New techniques such as VHDL and Basic Logic Elements are presented and applied to the proposed designs. The VHDL approach satisfies the highest optimization criteria in dynamic power at 87% for the sequential multiplier than the traditional ones.
- Different multiplication algorithms are implemented using Xilinx System Generator.
- A new approach is called the VHDL approach used for dynamic power minimization.
- The reconstruction method is used to implement the multiplication algorithms.
- The multiplication algorithms are realized on FPGA using the Xilinx Spartan 3A kit.
- Dynamic power dissipation is varied proportionally with the operating frequency.
 G. E. Moore, Cramming more components onto integrated circuits. McGraw-Hill New York, NY, USA:, (1965).
 T. L. Floyd, Digital Fundamentals. Pearson Education India, 2010.
 F. W. Wibowo, Comparison of multiplication algorithms based on FPGA, in 2018 2nd Borneo International Conference on Applied Mathematics and Engineering (BICAME), (2018) 326–331.
 Y.-J. Chang, Y.-C. Cheng, S.-C. Liao, and C.-H. Hsiao, A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism, IEEE Access, 8(2020) 114842–114853.
 D. Nandan, J. Kanungo, and A. Mahajan, An efficient architecture of iterative logarithm multiplier, Int. J. Eng. Technol.,7 (2018) 24–28, doi: 10.14419/ijet.v7i2.16.11410.
 B. Mukherjee and A. Ghosal, Design and Analysis of a Low Power High-Performance GDI based Radix 4 Multiplier Using Modified Booth Wallace Algorithm, in 2018 IEEE Electron Devices Kolkata Conference (EDKCON), (2018) 247–251.
 N. F. Afreen, M. M. Basha, and S. M. Das, Design and implementation of area-delay-power efficient CSLA based 32-bit array multiplier, in 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), (2017) 1578–1582.
 S. Kakde, S. Khan, P. Dakhole, and S. Badwaik, Design of area and power aware reduced Complexity Wallace Tree multiplier, in 2015 International Conference on Pervasive Computing (ICPC), (2015) 1–6.
 H. P. Patil and S. D. Sawant, FPGA Implementation of conventional and vedic algorithm for energy efficient multiplier, in 2015 International conference on energy systems and applications, (2015) 583–587.
 K. R. Varma and S. Agrawal, High speed, Low power Approximate Multipliers, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), (2018) 785–790.
 R. Mudassir, M. Anis, and J. Jaffari, Switching activity reduction in low power Booth multiplier, in 2008 IEEE International Symposium on Circuits and Systems, (2008) 3306–3309.
 K. Paulsson, M. Hübner, and J. Becker, Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems, Microprocess. Microsyst., 33 (2009) 46–52, 2009.
 I. A. Hashim, An FPGA Based a Digital Circuit Design for Route Optimization, Eng. Tech. J., 30 (2012).
 I. A. Hashim, Design and Implementation of a Two Stage Controller for Ball and Beam System Using FPGA, Eng. Technol. J., 36 (2018).
 I. Kuon and J. Rose, Measuring the gap between FPGAs and ASICs, IEEE Trans. Comput. Des. Integr. circuits Syst., 26(2007) 203–215.
 N. P. Kumar, B. S. Charles, and V. Sumalatha, A Review on Leakage Power Reduction Techniques at 45nm Technology, Mater. Today Proc., 2 (2015) 4569–4574.
 A. Pal, Sources of Power Dissipation, in Low-Power VLSI Circuits and Systems, Springer, (2015) 141–173.
 R. Y. Reetu, Dynamic power reduction of VLSI circuits: a review, Int. J. Adv. Res. Electron. Commun. Eng, 7 (2018) 245–259.
 M.-B. Lin, Introduction to VLSI systems: a logic, circuit, and system perspective. CRC press, 2011.
 A. Ben Abdallah, Power Optimization Techniques for Multicore SoCs, in Advanced Multicore Systems-On-Chip, Springer, (2017) 225–244.
 M. Arora, The art of hardware architecture: Design methods and techniques for digital circuits. Springer Science & Business Media, 2011.
 A. Pal, Low-Power VLSI circuits and systems. Springer, 2014.
 S. Devadas and S. Malik, A Survey of Optimization Techniques Targeting Low Power VLSI Circuits Srinivas, 32nd ACM/IEEE Des. Autom. Conf., 1995.
 M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Trans. Very Large Scale Integr. Syst., 2 (1994) 426–436.
 E. Macii, M. Pedram, and F. Somenzi, High-level power modeling, estimation, and optimization, IEEE Trans. Comput. Des. Integr. circuits Syst., 17 (1998) 1061–1079.
 S. P. Mohanty, N. Ranganathan, E. Kougianos, and P. Patra, Low-power high-level synthesis for nanoscale CMOS circuits. Springer Science & Business Media, 2008.
 G. Verma, M. Kumar, V. Khare, and B. Pandey, Analysis of low power consumption techniques on FPGA for wireless devices, Wirel. Pers. Commun., 95 (2017) 353–364.
 W. Stallings, Computer organization and architecture: designing for performance. Pearson Education India, 2003.
 S. Srikanth, I. T. Banu, G. V. Priya, and G. Usha, Low power array multiplier using modified full adder, in 2016 IEEE International Conference on Engineering and Technology (ICETECH), (2016) 1041–1044.
 C.-C. Wang and G.-N. Sung, Low-power multiplier design using a bypassing technique, J. Signal Process. Syst., 57 (2009) 331–338.
 J. Qian and J. Wang, A 4-bit array multiplier design by reversible logic, in Information Technology: Proceedings of the 2014 International Symposium on Information Technology (ISIT 2014), Dalian, China, 14-16 October 2014, (2015) 5.
 Xilinx and Inc, Xilinx DS255 Multiplier v11.2, Data Sheet, 2011. Accessed: Mar. 09, 2021. [Online]. Available: www.xilinx.com1.
- Article View: 121
- PDF Download: 205