Implementing Fuzzy Logic Controller Using VHDL

Design of a Fuzzy Logic Controller (FLC) requires more design decisions than usual, for example rule base, inference engine, defuzzifiction, and data pre-and post processing. This paper describes a way to implement a simple (FLC) in VHDL, there are three parts to fuzzy controller, the fuzzification of the inputs, the defuzzification of the outputs

for design capture and VHDL-based logic synthesis are an efficient method for designing complex hardware.The fuzzifier and defuzzifier parts of the system, which incorporate a lot of mathematical computations, are described in VHDL as a hand-coded design.We assemble the fuzzy control system, and synthesize a gate level description for field programmable gate array (FPGA) technology.This paper is organized as follows: In section 2 we give a brief introduction to fuzzy controllers.Section 3 shows a proposed controller design description.Section 4 lists design choices made, and brings a description of the design flow.A fuzzifier, a defuzzifier and a rule-base of the controller are modeled in VHDL, as presented in section 5.The developed model is synthesized and implemented in section 6. Conclusions are presented in section 7.

2-Overview of Fuzzy Controllers
The fuzzy controller takes input values from the real world.These values are referred to as "crisp" since they are represented as a single number, not a fuzzy one.In order for the fuzzy controller to understand the inputs, the crisp input has to be converted to a fuzzy number.This process is called fuzzification.The next step in the fuzzy control process is the implementation of the rule base.This is where the fuzzy inputs are compared and on the membership of each, the fuzzy output is chosen.For a 2 input system with 5 membership functions for each input, there would be 25 fuzzy rules to compute since they are anded together.The final step is to convert the fuzzy outputs of the rule-base to crisp ones.This process is known as defuzzification.This process will take a fuzzy number and apply it to a membership function to achieve the crisp number that will be sent to the real world [5,6,7].

3-The proposed FLC
This section, introduces a simple controller system, which serves as an example to the various steps involved when designing a fuzzy controller.The controller is sensitive to two input variables (error (e) and change in error (ce)) and produces one output variable (control Action (u)).For each of these inputs and output, five symmetric and triangular-shaped membership functions are defined and evenly distributed on the appropriate universe of discourse.A membership function gives the degree of membership of an input value to every fuzzy set.The input may belong to more than one fuzzy set.In the example application, the error and change in error are divided into five overlapping fuzzy sets called "Large Positive", "Small Positive", "Zero", "Small Negative", and "Large Negative".

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The fuzzified input variables are input to the rule base, the sample controller uses 25 rules, displayed in Table (1) to find an output fuzzy set.In our implementation we used one of the most commonly used defuzzification methods which is the Center of Areas (COA), which is computationally expensive since it includes division.

4-Design choices, design flow and environment
We have implemented a dedicated fuzzy chip, capable of performing stand alone operations, rather than extend some general purpose processor with fuzzy instructions.Our decision is influenced by several facts: _ a dedicated chip offers the highest execution speed, _ design time is short, due to the usage of synthesis and high-level design tools, _ low cost of real-estate.
For designing three parts (fuzzier, rulebase, and defuzzier) of FLC, we have used a behavioral architecture of VHDL language approach that means encoding these parts directly in VHDL.The reasons for this choice are: _ it reduces the design time, _ global design functionality is evaluated in a short time, _ different design choices are quickly explored, _ edit-compile-debug cycle is fastened [8], _ it provides little or no insight into the physical implementation of the entity but provides very flexible code that can be modified quickly [9].
Modeling a rule base, a fuzzifier and a defuzzifier of a fuzzy control system perform mathematical operations, such as multiplications and divisions.For describing such parts, direct encoding in VHDL at the register-transfer level is more efficient in VHDL We have used field-programmable gate arrays (FPGAs) as hardware platform, because they are complex enough to be used for rapid prototyping of complex systems, and for the final implementation of a chip, if only a small number of pieces is needed.They offer more flexibility than ASICs, as when a design is not needed any more; the chip can be reprogrammed for a new hardware.For the purpose of design and implementation of this controller, a VHDL model describing the design operation is presented, this VHDL model uses Xilinx families (virtex2-x2v4000) FPGA [10], the model is verified and synthesized using analysis and compiled tools provided by ISE4.1 software.

5-VHDL descriptions of the fuzzy logic controller
The fuzzifier, the defuzzifier and the rule-base used in our fuzzy controller have been described in hand-optimized VHDL.Inputs to the fuzzifier are input variable, and outputs are variables containing membership degrees for all input fuzzy sets.A part of the VHDL description of a fuzzifier is given in Fig.
(1).In the architecture body, membership degrees of the input signal are calculated for each fuzzy set.The defuzzification is modeled in a similar way, a part of the VHDL description of the defuzzifier is listed in Fig. (2).The input is a membership set of variables and the output is the control variable.Fig. (3) shows part of the VHDL description of the rule-base of the controller, in the VHDL coded of the rule-base; if-then statement is used, which may be a more natural choice in the coding process, also each rule is represented in the distinct processes.

6-Synthesis and technology mapping
After design verification, the ISE4.1designcompiler is used to perform logic synthesis.The result of synthesis is a gate-level description of the controller.Fig.( 4) shows the results of synthesis of the example fuzzy controller with two input and one output variables, and a rule base consisting of twenty-five rules.We have compiled our models targeting technologies: Xilinx FPGAs (x2v4000).For FPGA implementation, the measure area efficiency is expressed in a number of CLBs (configurable logic blocks).

7-Conclusion
In this paper, we have presented approach for describing fuzzy logic controller using VHDL description and FPGA technology.The selection of a certain FPGA devices depends on many parameters like: number of input and output variables of the system, the cost and delay required in implementing the system and reprogramming capability.The Xilinx (x2v4000) FPGA device is the one suitable for implementing FLC because it satisfies all above mentioned requirements with reasonable optimization.The FLC based FPGA technology substantially simplifies the design loop.The result in some significant benefits, such as development time, simpler design and faster time to market.

Figure ( 1 )
Figure (1)A part of the VHDL description of a fuzzifier