Design and Implementation of Programmable FIR Filter Using FPGA

: This paper presents the design and implementation of a programmable Finite Impulse Response (FIR) Filter using ALTERA Field Programmable Gate Array (FPGA) device. The filter performance is first tested using Filter Design and Analysis (FDA) tool from Mathworks to verify magnitude response and obtain coefficient tables. The test operation includes LPF and BPF filter types with coefficient lengths of 7 and 31 respectively. The FPGA design is carried out by writing VHDL modules for different filter components. The simulation waveforms, synthesis reports and board programming files have obtained using the package QUARTUSII. ALTERA-FLEX10K10 FPGA Family with EPF10K10LC84-3 board is used as a target device for implementation purpose

FIRs have the advantage of being much more realizable in hardware [6] because they avoid division and feedback paths.FIR filter response y(n) is computed by convolution operation between filter coefficients h(k) and the input data x(k) which can be described by the following equation: where N is the number of filter coefficients.Upon performing convolution, one of the two sets of numbers is reversed and "slid past" the other.The resulting stream of numbers is found by taking the sum of the multiplications at each sliding interval.FIRs can be graphically represented by a Direct Form realization as shown in Figure 1.The process of designing a filter in an FPGA involves two distinct steps [7]: designing the filter response and designing the filter implementation.
Over 100 different filter design tools, including toolbox functions available in MATLAB, are available for designing filter response and generating coefficient tables, each with varying levels of sophistication.Graphical filter design tools provides easy-to-use selections for specifying passband, filter order, and design methods, as well as provide plots of the response of the filter to various standard forms of inputs.One of the most popular tool is the FDA tool from the MathWorks shown in Fig. 2 which generates a behavioral MATLAB model and coefficient tables.

III-FPGA Implementation of FIR
Filter: Using QUARTUSII software package provided by ALTERA [8], VHDL modules were written for each of filter elements.Fig. 3 shows the the schematic design which integrates all design modules (entities).These modules are taps, hvalues, state_m and acc.
The module taps receives the input data d(7..0) whose width is 8 bits and store them permanently on a shift register basis of width equals the number of filter taps.According    When all data values passed to the multiplier, the signal "newt " is activated to receive new data stream.
The hvalues module stores the coefficient values of the filter "h(2..0)" and push them to the multiplier sequentially also according to the selection signal produced by state_m module.Two other signals are produced by hvalues module: "first" to mark that the current multiplication operation is the first one along the convolution interval and "follow" to mark that all multiplications have been finished and a new stream would be ready to apply.
The accumulator module acc carry out addition process of individual multiplication results.The multiplier is designed directly from Mega Core design facility provided by QUARTUSII [6] package without the need of writing VHDL file manually.In the design, the D flip/flops provides the facility of store the produced values and obtain complemented output if necessary.

IV-Top-Level Design:
Using QUARTUSII software package provided by ALTERA, VHDL design modules are written for each of filter entities.At the top level of design, a schematic file is created to assign input and output pins as it look like in the ALTERA-FPGA chip.Fig. 8 shows the top level design file for the implemented FIR filter.

V-Verification of Filter Response:
In order to test the designed filter, it must first coefficient tables for each test operation being already available.With FDA tool provided by MathWorks, it is easy to obtain such tables for required performance.
The verification includes 7-tap and 31 tap low pass and bandpass filters.Each of filter frequency response and filter output signal plots have been included for further comparisons.The input signal includes a mix of four different sinusoids having the following frequencies: The frequency responses significantly differ between the two filter lengths where the 7-tap filter allows considerable energy for unwanted frequencies to pass Eng.&Tech.Vol.26,No.7,2008 Design and Implementation of Programmable FIR Filter Using FPGA 872 through.Whereas the 31-tap filter provides a sharper roll-off at the cutoff frequency and possesses sidelobes lower than the -20 dB mark.Fig. 5 illustrates the results of failing to provide a narrower transition band.Energy from the 250 Hz sinusoid were allowed to pass through the filter whereas the 31-tap filter completely eliminates the frequency.

■ Bandpass Filter Verification:
The bandpass filter attempts to only pass frequencies in the 180 Hz -270 Hz range.A significant difference between the two filter frequency responses can be seen where the 7-tap filter allows much more energy from unwanted frequencies to pass.In addition, the left sidelobe for the lower frequencies does not fall below the -20 dB mark.However, the 31tap filter provides much sharper roll-offs for both cutoff frequencies and exhibits a better sidelobe characteristic.

VI-Implementation Results: ■ Simulation :
Once the filter performance is verified and filter coefficient tables are obtained from FDA tool, the next step is to obtain simulation waveforms to verify the correctness of FPGA implementation.Fig. 9 shows a sample simulation waveforms for a 7-tap LPF whose magnitude response shown in Fig. 4. In Fig. 9, the clock period is chosen to be 20 nsec and the data d(7..0) are assumed an unsigned decimal count value start from 0 to 15 and repeats with an increment of one in each clock pulse.The "newt" signal is activated as shown from waveform after every eight successive clock pulses which means a stream of 8 bit data has been stored in the shift register.Since the result in a value of 11 bit length, the "fellow" signal is activated after 11 clock pulses and "yvalid" signal becomes 1 in the next clock cycle to indicate that a new result is available.1 through 4 show summary of hardware synthesis reports for 7-tap LPF, 31-tap LPF, 7-tap BPF and 31-tap BPF whose performances were discussed in section V respectively.It is seen from these reports summary that the FPGA resources requirements increases as the number of filter taps increases and as a result, the maximum possible operating speed decreases.However there is no significant difference in storage resources or speed when the filter type is changed for the same filter coefficient lengths.

Figure 1 :
Figure 1: Direct Form realization signal flow graph of an FIR.

Fig. 4 Fig. 5
Fig.4 Top-level design of the FPGA implemented FIR Filter.

Table 2
Summary of hardware synthesis reports for 31-tap LPF

Table 3
Summary of hardware synthesis reports for 7-tap BPF Maximum period 3.79 ns (Maximum frequency: 263.8 MSPS).Maximum path delay from the any node: 3.8 ns.

Table 4
Summary of hardware synthesis reports for 31-tap BPF Maximum period 11.22 ns (Maximum frequency: 89.1 MSPS).Maximum path delay from the any node: 11.22ns.