Design and Simulation of Sigma-Delta Fractional-N Frequency Synthesizer for WiMAX

This paper presents a design and simulation of proposed frequency synthesizer which can be used for WiMAX. Design parameters for the proposed fractional-N PLL synthesizer for WiMAX system are either selected from WiMAX standards or according to results of analysis for each unit of the proposed system. Different techniques for phase noise reduction are discussed. Sigma-delta fractional-N technique is chosen for WiMAX system, since low settling time, spurious level and phase noise can be obtained by using this technique. The simulation result shows the system is stable, since the phase margin is greater than 45 degree. The settling time, spurious level and phase noise obtained with this synthesizer are 5.9µs, -90dBc/Hz, and -100dBc/Hz respectively. CppSim program (C++ simulator language) and Matlab (V.7) are used for simulation of Σ∆ fractional-N PLL synthesizer


Introduction
WiMAX is a wireless metro-politan area network (WMAN) technology that provides interoperable broadband wireless connectivity to fixed, portable, nomadic and mobile users [1].It provides up to 50 Km of service area under line of sight (LOS) condition and up to 8 Km under non line of sight (NLOS), and provides total data rates up to 75 Mbps to support simultaneously hundreds of businesses and homes with a single base station.WiMAX improves the last-mile delivery aspects of multipath interference and delay spread [2,3].Multi-path interference and delay spread improve performance in situations where there is no direct line-of-sight (NLOS) path between the base station and the user station.However, common to almost all of these standards is that the data N f out / ), which is sent to the PFD.At the PFD, the phase and frequency of the signal are compared with an external signal of frequency ( f f Re ), which is generated using a crystal oscillator.The output signal of the PFD and CP is then low pass filtered, and the filtered signal is sent to the VCO input to control the frequency of the output signal [3].The disadvantage of this technique is the output frequency is equal to multiple of the reference frequency ), where N, the loop frequency divide ratio, is an integer.The frequency resolution of the integer-N frequency synthesizer is equal to the reference frequency [3].The conventional integer-N PLL with low reference frequency has several disadvantages.First, the lock time is long due to its narrow loopbandwidth.Second, the reference spur and its harmonics are located at low offset frequencies.Third, the large divide ratio (N) increases the in-band phase noise associated with the reference signal.Finally, with a small loop-bandwidth, the phase noise of the VCO will not be sufficiently suppressed at low offset frequencies [3].The most well accepted solution to these problems [3] is the fractional-N PLL that is discussed in next section.

2.
Fractional-N Frequency Synthesizer In integer-N synthesizer, the minimum resolution is equal to the reference frequency.In order to get a finer resolution, a fractional-N technique is used to achieve frequency resolution finer [5,6] than the reference frequency, as shown in The main source of problems in fractional-N synthesizers is when an overflow occurs in the accumulator, the divider ( ) is divided by N+1 for one period, corresponding to a 2π decrease in the phase error at the phase detector input, as shown in Figure (2b).The resulting phase error causes spurious tones at the output frequency [5].

Spur-Suppression Techniques
The classical approach to fractional-N synthesizer design [5,7] employs dithering and phase interpolation (PI), as shown in Figure (3).An accumulator carry-out signal is used to dither the control input to a multi modulus divider.The DAC is used to convert the instantaneous phase error, which is proportional to the residue of the accumulator, into an equivalent amount of charge-pump current to compensate the phase error [7].The main limitations with this architecture center around the achievement of a good matching between the DAC output and phase-error signal.This matching is difficult to obtain because the two signals are processed by separate circuits whose outputs are summed.Any gain mismatch between PFD error and DAC output will lead to spurious tones at PLL output.The second technique uses a sigmadelta modulator.This technique is based on oversampling and noise shaping to reduce the phase noise [5,6,8].The quantization noisebandwidth tradeoff associated with Σ∆ fractional-N synthesis can be removed if quantization noise can be reduced.The combination of PFD and DAC in one single element is used to overcome non-idealities between them, as shown in Figure (4).
The key advantage of this method is that the circuitry that injects quantization noise into the loop (the PFD and charge-pump) is combined with the cancellation signal by DAC to create an inherent gain match between the two signals.7) shows the simulation results of Σ∆ MASH modulator.The quantization noise of first Σ∆ modulator is perfectly cancelled by using the second order digital Σ∆ modulator.However, the third order Σ∆ MASH is suggested to eliminate quantization noise.Simulation results show an improvement of 149 dB in signal-to-noise ratio (SNR) at the output of the third order Σ∆ modulator (which is used to control DAC elements) instead of 109.3 dB for the second order Σ∆ modulator, as shown in figure (7)..12)

Phase Noise Simulation
Figure (2a).The output frequency out f can be varied in fractional increments of reference frequency.The fractional part of divider is Eng.&Tech.Vol 26,No.9,2008Design and Simulation of Sigma-Delta Fractional-N Frequency Synthesizer for WiMAX implemented using phase accumulator [5].
Figure (8) presents the result of simulation.In this simulation, the reference spur magnitude is -90dBc/Hz.A sample-and-hold (S/H) is used to eliminate shape mismatch related spurs as shown in simulation results in Figure (9) (if compared with the simulation results shown in Figure (8)).
Figure (1): The block diagram of phase-locked loop.