Authors
Abstract
One of the major constraints on hardware implementations of Artificial Neural
Networks (ANNs) is the amount of circuitry required to perform the multiplication
process of each input by its corresponding weight and there subsequent addition. Field
Programmable Gate Array (FPGA) is a suitable hardware IC for Neural Network (NN)
implementation as it preserves the parallel architecture of the neurons in a layer and
offers flexibility in reconfiguration and cost issues. In this paper the adaption of the
ANN weights is proposed using Particle Swarm Optimization (PSO) as a mechanism
to improve the performance of ANN and also for the reduction in the ANN hardware.
For this purpose we modified the MATLAB PSO toolbox to be suitable for the taken
application. In the proposed design training is done off chip then the fully trained
design is download into the chip, in this way less circuitry is required. This paper
executes four bit Arithmetic Logic Unit (ALU) implemented using Xilinx schematic
design entry tools as an example for the implementation of digital circuits using ANN
trained by PSO algorithm.
Keywords
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