Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software Defined Radio

This paper presents a design and simulation of digital PLL synchronizer, using Costas loop based on SDR for high fr equency communication systems. D esign parameters a re selected fo r e ach unit of the proposed systems in order to accommodate SDR requirements. Different techniques for carrier recovery based on SDR are discussed. P LL techniques is chosen for synchronization, since it is one of the most a ctive sync hronization techniques. BPSK and QPSK synchronizers for coherent receivers have b een designed and simulated based on SDR using b oth Costas loop and m odified Costas loop. The si mulation result shows th at t hese two systems a re reliable in r ecovering th e ca rrier phase and frequency when significant fre quency a nd p hase are p resent. Simulation result shows th at t he BPS K syst em has e P = 3 10 - at o b N E / equal to 8 .5 dB i n the presence of AWGN and has the ability to tra ck frequency offset up to 1200H z with 2*10 4 - probability of bit error at o b N E / equal to 20 dB. Th is system can track phase offset 45 o with e P = 4 10 - at o b N E / equal to 20 dB. For QPSK system, the probability of bi t error 3 10 - at o b N E / = dB 9 and has the a bility to track frequency offset 300 Hz a nd phase offset=9 o with e P = 3 10 - at o b N E / equal to 20dB.


Introduction
Wireless communications is the fastest growing segment of the communications industry.The vision of wireless communications supporting information exchanged between people or devices is the communications frontier of the next century.This vision will allow people to operate a virtual office anywhere in the world using a small handheld device with wireless devices [1].Traditional wireless devices are designed to deliver single communication service using a particular standard [2].It is expensive to upgrade and maintain a wireless system each time a new standard comes into existence.Wireless systems are gravitating towards minimal radio hardware designs using flexible architecture software radio (SR) [3].Software defined radio (SDR) is a collection of hardware and software technologies that enable reconfigurable system architectures for wireless networks and user terminals to reduce the amount of analogue signal processing in radio applications, by implementing the conversion between analogue and digital signals as close to the antenna as possible, and then performing signal processing operations in the software domain [2].SDR can be viewed as an adaptive solution for making wireless networks highly flexible [4].The concept of SDR has initially been discussed for military applications.Today, with the increase of the digital signal processor (DSP) capabilities on the one hand and the requirements for rapid deployment to market on the other, SDR is emerging as an important commercial technology.It brings together two key technologies of the last decade: digital radio and downloadable software [5].Over time the number of system components performed in software is increasing.Figure (1) depicts the evolution from Hardware (HW) to SDR to SR to "Adaptive Intelligent-Software Radio" (AI-SR) [3].
Synchronization is one of the most difficult problems for the communication systems.The phase and frequency offsets are the critical problems for the data detection that lead to severe performance degradation especially when higher order modulation is applied.These two offsets can be compensated by using phase locked loop (PLL) which represents the heart of nearly all synchronization systems.PLL has a relatively simple structure composed of phase detector, loop filter and voltage Controlled Oscillator (VCO) [6].An important technique is the combination of two quadrature loops to form Costas loop which are discussed in the next sections.

Phase locked loop (PLL) 2.1 Analog PLL
The heart of nearly all synchronization systems is some version of phase locked loop (PLL) [6].Analog PLL consists of three components [7,8] (PD), the loop filter (LF) and the voltage controlled oscillator (VCO).The function of PD block is to compare the phases of the input and output signals and generate an error signal proportional to the phase deviation between them.There are two forms of phase detector which are the analog PD and digital PD.Basically analog PD functions as a mixer with an IF centered at zero frequency [9], while digital PD are based on applications of simple flip-flop gates or more complicated combinations.Low-pass filter is used to remove the high frequency terms that comes from the output of the PD [10].The selection of the loop filter is a very important decision, since it will determine the behavior and characteristics of the PLL under various operating conditions such as bandwidth, lock-in range, pullin range, pull-out range and hold-in range of the PLL during operation [11].Active low pass PI filter was selected due to its great performance and its stability [8].The final component is the VCO which is a device that produces the carrier replica i.e. a sinusoidal oscillator whose frequency is controlled by the input voltage [6].The control voltage from the loop filter adjusts the frequency and phase of the VCO to synchronize with the input signal's frequency and phase.In the locked state the frequency difference and the phase difference between the input signal and the output signal from the VCO is zero.This means that the PLL replicates a signal whose frequency and phase are exactly the same as those of the input signal [10].

Digital phase locked loop (DPLL)
DPLL are attracting more attention for the significant advantages of digital systems than analog PLL.These advantages include superiority in performance, speed, reliability, and reduction in size and cost.DPLL reduced many problems associated with APLL [12].Figure (2) shows the digital form of PLL.In DPLL the VCO is replaced with digital direct synthesizer (DDS), the loop filter is digitized and is converted to IIR filter and finally the PD converted from a simple mixer to digital PD.There are four types of digital PD: Flip-Flop DPLL, Nyquist-rate DPLL, lead-lag DPLL, exclusive-OR DPLL and zerocrossing DPLL [13,14].In this paper the flip-flop DPLL is used to provide the phase and frequency output error signal.

Carrier recovery
Synchronization is one of the fundamental functions in communication systems.Its task is to lock the synchronization parameters of the receiver with the received signal.Most receivers require three main synchronization levels: carrier synchronization, symbol synchronization and frame synchronization [6].Estimation of synchronization parameters is very essential for performing demodulation and detection of the data from the transmitted signal with high reliability.
In almost every receiver or demodulator performance, some level of signal synchronization is generated.In the case of binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) demodulation, the receiver is assumed to be able to generate reference signals whose phases are identical to those of the signaling alphabet at the transmitter [6,15,16]

System Description
The BPSK Costas loop block diagram [6] is depicted in figure (3).The BPSK signal is first generated at the transmitter, then after the multiplier, passed through the arm filters in order to suppress the higher order components and the low order components is passed then the two filtered signals is passed through the loop filter which is the lead-lag type.The signal that leaves the loop filter then is passed through the VCO to generate the carrier signal necessary for synchronization purposes.For QPSK signal, the modified Costas loop [8,18] is used in order to accommodate the QPSK requirements as shown in figure (4).The design parameters of the system are shown in table (1).Design parameters are either selected from the design standard requirements or according to results analysis of each system unit.

Description of the Designed system components 5.1 Design of Loop Filter
The analog PI filter is used as mentioned due to its stability in canceling the error that comes from the multiplication process.This filter generates the VCO control voltage according to the error from the multiplication.The transformation from S-domain to Z-domain is used in the design of the loop filter as shown below.The design parameters of the loop filter is shown in table (2).The transfer function of the PI filter is [8]: The relation between Z and S is [8,11]: Substituting equation ( 2) by ( 1) yields:- From the 2 nd order PLL relation [7,8]: , where a is a constant such that a > 2 [8,11].This relation was obtained by calculating the 3−dB frequency of the loop filter [8]: Gardener [7] suggests that there is a relation between Substituting by equation ( 4) yields:

Phase Detector Design
The tri-state-based flip-flop DPLL consists of two D flip-flops with additional logic to reset the latches is chosen.The PFD generate pulses to steer the VCO frequency either up or down.Any mismatch between the up and down paths of its output degrades the linearity of its phase error characteristic.The PFD output depends on the phase error and the frequency error [16,17].

Design of VCO
In the digital domain, the VCO is replaced by the digital direct synthesizer (DDS) [14].In this paper the DDS is used in the SDR synchronizer system as shown in figure (5).The characteristics of the DDS are shown in table (3).

Design of arm filter
The arm filter is a low pass filter in order to remove the high frequency components that come from the multiplication of the received signal and the VCO signal for both I and Q channels.In this paper the FIR filter is chosen in the design because it has linear phase response [19].The characteristic of this filter is shown in table (4).The Hamming window is selected in the design.The transfer function for this filter is given by [8]:- The hamming window takes the form [8]: Where:-N is the filter order ) (n h is the impulse response, n=0,1,…N-1

PLL measurements
Figure ( 6) represents the flow chart of the designed system.Figure (7) shows the simulation results of general PLL block diagram when there is 10 deg.phase offset between the input and the DDS signals.Figure (8) represents the loop filter output for 10 deg.Offset.

BPSK system simulation results
The performance of the designed system will be evaluated by plotting the probability of bit error (P e ) versus the  8) and for QPSK is:- Q is the error function.
Figures (9,10 and 11) Figure (20) shows the simulation results of the QPSK system with different frequency offsets from the ideal case starting from the 0 offset up to 1000Hz frequency offset.Figure (21) shows the simulation results of the QPSK system with different phase offsets from 2 o to 18 o .Figure (22) shows the cases when 50Hz frequency offset and variable phase offsets (0 o to 18 o ).

Discussion of simulation results
1.The designed BPSK system has a probability of bit error equal to

Conclusions
The conclusions of this work can be summarized as follows:-1.The carrier recovery technique based on SDR presented in this paper proved to be applicable to the modulation schemes of M-PSK signals.Simulation has shown that frequency and phase estimation can be implemented by using feedback structures (Costas loop) with a large estimation range and good performance.In order to obtain PDF created with pdfFactory Pro trial version www.pdffactory.com

Bandwidth (BW) 5MHz
Hamming window is used Because of its simplicity and for its accuracy in the presence of AWGN and has the ability to track frequency offset up to 1200Hz with 2SDR, PLL, Synchronization, Carrier recovery, Costas loop.
designed BPSK system has the ability to track the phase and frequency offsets in specified ranges extending from 50 Hz and 5 o with P e =10 4 − at E b /N o =15 dB up to 1000Hz and 9 o with P e =10 3 − at E b /N o =19 dB which shows the loss in E b /N o as a penalty that may be paid to overcome the offsets.4. The designed QPSK system has a probability of bit error=10 5 − at 12 dB without any offset.5.The designed QPSK system can track the phase offset up to 9 degree phase offset with a probability of bit error designed QPSK system has the ability to track the simultaneous frequency offset and phase offset in the range from 50Hz and 2 o offsets with P e

com Eng.& Tech. Journal ,Vol.27, No.10, 2009 Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software defined radio 2010
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& Tech. Journal ,Vol.27, No.10, 2009 Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software defined radio
PDF created with pdfFactory Pro trial version www.pdffactory.comEng.

Eng.& Tech. Journal ,Vol.27, No.10, 2009 Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software defined radio
PDF created with pdfFactory Pro trial version www.pdffactory.com

& Tech. Journal ,Vol.27, No.10, 2009 Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software defined radio
show the P e versus PDF created with pdfFactory Pro trial version www.pdffactory.comEng.