This paper focus on represent and implementation the conventional sliding mode control (SMC), in addition to some types of the common enhancement SMC approaches using reconfigurable hardware technology based on Field Programmable Gate Arrays (FPGAs); this is because FPGAs are highly attractive options for hardware implementation. The enhancement SMC approaches that used here are:1) the conventional SMC with boundary layer, 2) PI sliding mode controller, and 3) boundary SMC with new approximation sign function. The main key of this work is to
implement these SMC approaches in high volume FPGA devices, a low area and fast clock speed device, where these approaches are implemented in Xilinx Vertix family Xcv1000-fg680-4 FPGA (the occupation rate is 86% and maximum net delay is 0.032 ns). All the architectures in VHDL, verified the functionality using Active-HDL simulator, and synthesis the data paths using ISE 4.1i software package synthesis tool
and Xilinx place and route tool of this package. Finally, to test the performances of the enhancement SMC approaches, computer simulation is performed on linear and nonlinear system models in order to compare the performance of these SMC approaches to illustrate which approach between them give more efficient performance than the others