Implementing of Forward Link Channel CDMA2000-1x System by Using Simulink HDL Coder

This work is a proposed simulation for forward link channel of CDMA2000 -1x system by using QPSK, 8QAM and 16QAM, and converting the proposed system to VHDL language by using Simulink HDL Coder for implementing in FPGA board. The results of simulation for forward link channel of CDMA2000 system shows improvement when using three levels of codes (LPNC, Walsh code and complex coding) in the present of AWGN for QPSK modulation the system performance is improved from (1.8 to 1.9) in dB for BER (Bit Error Rate) 10 to 10 and for 8QAM the system performance is improved at (2.9) in dB for BER 10 to 10 and for 16QAM the system performance is improved from (1 to 1.2) in dB for BER 10 to 10 . The results of simulation in the present of AWGN and Rayleigh fading channel are improvement within (0.5) in dB for the different Doppler Frequencies (5 - 230Hz). The Simulink HDL Coder has been used for converting the MATLAB-Simulink models to VHDL language. The verification of the generated VHDL code has been done using Altera-ModelSim program, while the synthesis reports and board programming files have been obtained using the Quartus II program. System implementation has been done using FPGA technology with Altera Cyclone II boards. The implementation of the forward link channel by using Simulink HDL coder shows feasibility and flexibility in solving the problem of complex multiplication of complex spreading code also the practical results were closed to that obtained from ModelSim program.


INTRODUCTION
irect sequence CDMA (DS-CDMA) is the most popular of CDMA techniques.The DS-CDMA transmitter multiplies each user's signal by a separate code waveform.The signals of all users overlap and interfere with each other in a DS-CDMA system; the receiver recovers the signals by correlating the combined signal with the code of the desired user [1].
The third generation CDMA came through a detailed proposal process from vendor's interested in the evolution of IS-95B.The IS-95B standardization adopted a framework that combined the different vendor's proposals and later became known as CDMA2000.CDMA2000-1x is a family of 3G mobile technology standards, which use CDMA channel access, to send voice, data, and signaling data between mobile phones and cell sites.The set of standards includes: CDMA2000-1X, CDMA2000-EV-DO, CDMA2000-EV-DV, and CDMA2000-3x [2].However, implementing of CDMA2000-1x system with flexibility remains the main problem to born the practical system.MathWorks introduced Simulink HDL Coder, which automatically generates synthesizable Hardware Description Language (HDL) code from models created in the company's widely-used Simulink and Stateflow software.The product produces target-independent Verilog and VHDL code and test benches for implementation and verification by using FPGA.Simulink HDL Coder accelerates the design, implementation, and verification of hardware, by providing a path directly from system models to programing FPGA.Simulink HDL Coder also generates Verilog and VHDL test benches that enable reusing system simulation data for verification of the implemented design [3].

PROPOSED SYSTEM DESIGN
The proposed design procedure for FFCH-DS-CDMA2000-1x is shown in figure (1) and table (1) shows the proposed design parameters of the system.The main parts of the proposed system are in the following sections.

Long PN Code Design
Pseudo-Noise (PN) code sequence acts as a noiselike (but deterministic) carrier used for bandwidth spreading of the signal energy.The selection of a good code is important, because type and length of the code sets bounds on the system capability.The PN code sequence is a Pseudo-Noise or Pseudo-Random sequence of 1's and 0's, but not a real random sequence (because periodic).Random signals cannot be predicted.Maximal length sequences (which are also called msequences, pseudo random sequences or pseudo noise sequences) are certain binary sequences of length [4].
Where n = number of shift register.The long code in CDMA2000 consists of 42 shift register with mask (2 − 1), the recursion for the long code spreading is generated by the characteristic polynomial p(x) [4,5]: P(x) =x +x +x +x +x +x +x + x + x + x +x + x +x +x +x +x + x +x +x +x+1+ 1 (2)

Walsh Code Design
Walsh codes are the most common orthogonal codes used in CDMA applications.The Walsh codes are generated in a set of codes with length (N= 2 ).The generating algorithm is given by [5]: The rows (or columns) of the matrix W are the Walsh codes.In each case the first row (row 0) of the matrix consists entirely of (1s) and each of the other rows contains N/2 of (0s) and N/2 of (1s).The distance (number of different elements) between any pair of rows is exactly N/2.Each sequence of n bits identifies one row of the matrix (there are N=2 possible rows).All rows are mutually orthogonal [5].

Short Code Design ( and )
The short code is generated by a 15-stage shift-register circuit (2 − 1) chips arranged to produce the polynomials given by equations ( 5) and (6).Each of the circuits generates 32767 chip long sequences (2 −1) composed of 16384 '1s' and 16383 '0s'.The transmission rate of these sequences is 1.2288 Mcps, the sequence has a repetition rate of 37.5 times per second (1228800 cps/32768cps = 37.5 times/s) [4,5].

Digital Arm Filter Design
Raised Cosine Filter is used in order to remove the high frequency components from the output of multiplier.The two digital arm filters in transmitter must have the same design to avoid jitter and the order is not too high because that means delay.Table (2) shows the parameters selected for the filter.This filter will be FIR filter because it has linear frequency response [6].The transfer function is given by: The frequency response is given by: where ( ) is the impulse response of the FIR filter, the hamming window is given by [6]: Where = , , ,……….. − , ( ) is the window function, ( ) is the desired impulse response of the filter, is chosen proportional to sampling rate, M is the filter order.

Modulation Technique
Multilevel Quadrature Amplitude Modulation (M-QAM) is used in CDMA2000-1x to obtain higher spectral efficiency, which potentially results in higher throughput of packetized data.The QAM signal points lie in rectangle or square instead of circle as in QPSK.In QAM modulator both the amplitude and the phase of the bandpass signal will be changed, so it's PSK and ASK occur at the same time.The M-QAM signal is given by [7]: Where: ( )[cos(∅ ( ))] represent the amplitude of I-channel, ( )[sin(∅ ( ))] represent the amplitude of Q-channel and is the carrier frequency and t is the time.
Multilevel Quadrature Amplitude Modulation (M-QAM) extends QAM by making the size of the transmitted constellation variable.The variable constellation size means that the number of bits per symbol is also variable.The number of bits that can be sent per symbol, N, in a square constellation is related to M as N =log M (where M = number of levels) (also number of bits increases) the information can be sent also increases as long as the symbol rate remains constant.This leads to the possibility of variable bit rate operation in a constant bandwidth [7].

Decision Circuits
The probability of error depends on the characteristic of decision circuit.There are two types of decision circuit hard and soft.In Hard Decision Decoding (HDD) each coded bit is demodulated as 0 or 1, the demodulator detects each coded bit (symbol) individually.The received symbol is decoded as 1 if it is closer to /2 (E is energy per bit) and as 0 if it is closer to -/2.Soft decision is the second method of implementation in which the detector outputs a multilevel voltage and the channel decoder bases its output on these inputs.Soft decision provides about 2-3db coding gain over hard decision but increases the system cost because it requires an error correction code which means more complication and more cost [8].
In this work hard decision is used for QPSK because hard decision has the ability to distinguish between small amplitudes bits, and soft decision is used for M-QAM modulation to distinguish between large amplitude bits.Figures (2)

SIMULATION RESULTS
In this work the simulation of the proposed CDMA2000 system in the presence of Additive White Gaussian Noise (AWGN) and Rayleigh fading channel.
Different modulation types are used (QPSK, 8QAM and 16QAM) in the proposed system.A MATLAB (2009) is used in the simulation and performance evaluation of the proposed system.
Simulation Results for the Proposed System without Codes includes the performance evaluations of the different modulation / demodulation schemes which are used in the proposed system (QPSK, 8QAM and 16QAM) with AWGN and Rayleigh.In this stage of the simulation and the variation of the Bit Error Rate (BER) are performed according to the variation ratio for energy of data bit to the power spectrum density (E /N ). Figure (4) shows the performance of modulation over AWGN without codes and figures (5, 6 and 7) show the performance of modulation with (QPSK, 8QAM and 16QAM) without codes over AWGN and Rayleigh fading channel with different values of Doppler frequencies.
The performance of CDMA2000 using QPSK modulation system will be evaluated by plotting the BER versus the (E /N ) in the presence of AWGN and Rayleigh fading for different values of Doppler frequencies.Figure (8) shows the effect of AWGN over QPSK modulation and figure (9) shows the effect of AWGN and Rayleigh fading channel on the system.
The performance of CDMA2000 using 8-QAM modulation system will be evaluated by plotting the BER versus the (E /N ) in the presence of AWGN and Rayleigh fading for different values of Doppler frequencies.Figure (10) shows the effect of AWGN over 8-QAM modulation and figure (11) shows the effect of AWGN and Rayleigh fading channel on the system.
The performance of CDMA2000 using 16-QAM modulation system will be evaluated by plotting the BER versus the (E /N ) in the presence of AWGN and Rayleigh fading for different values of Doppler frequencies.Figure (12) shows the effect of AWGN over 16-QAM modulation and figure (13) shows the effect of AWGN and Rayleigh fading channel on the system.

IMPLEMENTING OF FFCH-DS-CDMA2000-1X BY USING SIMULINK HDL CODER
The proposed system has been designed and implemented based on Simulink HDL coder using FPGA.MATLAB-Simulink is used as an attractive simulation tool which provides the designer with many facilities such as fast design, and procedure test.Also, it gives the designer a clear imagination of the system parameters required to complete the design.MATLAB-Simulink of MATLAB ( 2009) is used in this work.Simulink HDL coder is a tool, which comes with MATLAB-Simulink software package and can be used to generate Hardware Description Language (HDL) code based on Simulink models and Stateflow finitestate machines.In this work, the design is first implemented in MATLAB-Simulink environment.It is then converted to VHDL level using the signal compiler block of the Altera-DE2-70 Board.The design is synthesized and fitted with Quartus II software, and downloaded to Altera-DE2-70 development board.

Setting Parameters
To start the implementation of the proposed system, the parameters of the proposed system should first be set, system parameters setting include specification of the different types of codes, modulation/demodulation and other related system operations that the SDR could handle.

Verifying Design Functionality
Some MATLAB-Simulink blocks, especially those that contain complex functions could not be converted to VHDL codes.To solve this problem, these blocks are redesigned using their basic components such that they could be converted to VHDL codes.
The modulations and demodulations are designed using embedded MATLAB functions (m-files), while other blocks are designed by MATLAB-Simulink blocks supported by Simulink HDL coder.

Generating Vhdl Codes For Matlab-Simulink Using Simulink Hdl Coder
Simulink HDL Coder compatibility checker utility can be run to examine MATLAB-Simulink model semantics and blocks for HDL code generation compatibility, then by invoking the coder, using either the command line or the graphical user interface.The coder generates VHDL or Verilog code that implements the design embodied in the model.Usually, a corresponding test bench can also be generated.The test bench with HDL simulation tools can be used to drive the generated HDL code and evaluate its behavior.The coder generates scripts that automate the process of compiling and simulating the code in these tools.

Verifying Design Functionality Using (Modelsim Tool)
The correct functionality of SDR is verified using Altera / Mentor Graphics ModelSim (6.5b) simulation tool.For this purpose, the test bench codes are compiled and simulated using the generated compilation and simulation scripts by the HDL coder.

Designing Synthesis using Quartus II
Designing Synthesis is a process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a lower level of logic abstraction using a library of primitives [9].

Downloading Bit Stream File to FPGA Boards
The synthesis process would also produce a bit stream file that can be downloaded in the FPGA board.The bit stream file of the SDR has been successfully downloaded to Altera-Cyclone II FPGA family boards, which is Cyclone II DE2-70.The test operation of the physical functionality of the SDR has been done by simply interfacing a function generator to apply input data and oscilloscope to monitor the recovered data.

DISCUSSIONS OF RESULTS
The performance of the proposed system in the presence of AWGN and Rayleigh fading channel shows improvements compared with the system without long-PN code, Walsh code and complex system as follows: v For simulation 1) For FFCh-DS-CDMA2000-1x by using QPSK modulation: • For BER 10 with AWGN, the system performance is improved by (2) dB.• For BER 10 with AWGN, the system performance is improved by (1.8) dB.• For BER 10 with AWGN, the system performance is improved by (1.9) dB.• For BER with DF= (5, 45, 90,160 and 230) Hz the system performance is improved by (0.5) dB. 2) For FFCh-DS-CDMA2000-1x by using 8QAM: • For BER 10 with AWGN, the system performance is improved by (3.1) dB.• For BER 10 with AWGN, the system performance is improved by (2.9) dB.• For BER 10 with AWGN, the system performance is improved by (2.9) dB.• For BER with DF = (5, 45, 90,160 and 230) Hz the system performance is improved by (0.5) dB. 3) For FFCh-DS-CDMA2000-1x by using 16QAM: • For BER 10 with AWGN, the system performance is improved by (0.8) dB.• For BER 10 with AWGN, the system performance is improved by (1.2) dB.• For BER 10 with AWGN, the system performance is improved by (1) dB. 1) The experimental results obtained from the implanted system using HDL coder show the flexibility of implementing the forward channel CDMA2000 system.
2) The problem of implementing complex multiplication was solved during this work by converting the complex multiplication to the ordinary multiplication by using m-file.This problem is considered the main difficulty in the published literature.

CONCLUSIONS
The following points represent the main conclusions obtained from this work: 1) The simulation results of FFCh-SC-DS-CDMA2000-1x system show improvements when using three levels of codes (LPNC, Walsh code and complex coding) within (0.5-2.9) E N ⁄ in (dB) in the presence of AWGN and Rayleigh fading channel.
2) The implementation of the forward link channel using Simulink HDL coder shows feasibility and flexibility of solving the problem of complex multiplication of complex spreading code also the practical results were close to that obtained from ModelSim program.3) Simulink HDL coder is very helpful for system engineers since the coder automates the hardware implementation process.Simulink HDL coder does not support all MATLAB-Simulink blocks, so to generate VHDL codes for such blocks they must be redesigned according to their basic design blocks supported by Simulink HDL coder.PDF created with pdfFactory Pro trial version www.pdffactory.com

and ( 3 )
show the soft and hard decisions block diagram respectively.
Figure (14) shows the Photograph of the FPGA board and figure (15) shows the Altera-DE2-70 development board.The implementing of the proposed system according to the following steps:

Figure ( 16 )
shows the input and output waveforms of the proposed CDMA2000 system with QPSK modulation by using ModelSim program and figure (17) shows these input and output data from an oscilloscope.

Figure ( 18 )CDMA2000 system with 8 -
shows the input and output waveforms of the proposed PDF created with pdfFactory Pro trial version www.pdffactory.comEng.& Tech.Journal, Vol.30, No.QAM by using ModelSim program and figure (19) shows these input and output data from an oscilloscope.Figure (20) shows the input and output waveforms of the proposed CDMA2000 system with 16-QAM by using ModelSim program and figure (21) shows these input and output data from an oscilloscope.

Figure
Figure (12): Simulation results of Figure (13): Simulation results of CDMA2000 by using 16QAM over CDMA2000 by using 16QAM over AWGN.AWGN and Rayleigh.

Figure ( 18 ):
Figure (18): Input and output waveforms of the CDMA2000 system with 8-QAM in ModelSim program