A VHDL Model for Implementation of MD5 Hash Algorithm

With the increase of the amount of data and users in the information systems, the requirement of data integrity is needed to be improved as well, so the work has become necessary independently. One important element in the information system is a key of authentication schemes, which is used as a message authentication code (MAC). One technique to produce a MAC is based on using a hash function and is referred to as a HMAC.MD5 represents one efficient algorithms for hashing the data, then, the purpose of implementation and used this algorithm is to give them some privacy in the application. Where they become independent work accessories as much as possible, but what is necessary, such as RAM and the pulse generator. Therefore, we focus on the application of VHDL for implement and computing to MD5 for data integrity checking method and to ensure that the data of an information system is in a correct state. The implementation of MD5 algorithm by using Xilinx-spartan-3A XCS1400AFPGA, with 50 MHz internal clock is helping for satisfies the above requirements.


INTRODUCTION
ith the increase of the amount of data and users in the information system, the requirement of data integrity is needed to be improved as well.So it was imperative for the designers of information security to take many measures to protect private data and systems from the early days [1].While the information security and the message authentication is an essential technique to verify that received message come from the alleged source and have not been altered.A key element of authentication schemes is the use of a message authentication code (MAC).One technique to produce a MAC is based on using a hash function and is referred to as a HMAC.Message Digest 5 (MD5) is one of its algorithms [2].

RELATED WORK
In the existing technical literature, many related, studies from the implementation point of view, the main are focused in three directions these are; Pure Hardware by Xilinx, Mixed Hardware with Software by use GPU and pure software; these are; In hardware direction; [3] present a FPGA implementation of MD5 modules, besides the internal parallel easily to duplicate and connected to Ethernet LAN.His built on Cyclone II EP2C35F672C6, for a single board, a throughput of 4.3Gbps was achieved with 30,134 logic elements are used.An extensive study of effects of pipelining on delay, area requirements and throughput is performed.The design was carried out on a Xilinx Virtex-II XC2V4000-6 FPGA, and a throughput of 586 Mbps was achieved with logic requirements of only 647 slices and two Block RAMs was made by [4].
In the GPU(mixed) direction;[5] was focused his work on the application of GPU (Graphical Processor Unit) for speedup the processing time.His implementation was based on 64 bytes with shift 112 left and 64 rights, then gained 16 times speedup over CPU but loses the independence.The IPSec protocol stocks for micro server are proposed by [6].Protocol authentication was worked by MD5 with 2.144 Kbyte in 2.704 Kbyte IPSec Protocol.The good-point in his work is the mixing between the commercial and security requirements.[7]was built the cloud data server with session controller architecture to satisfy MD5 algorithm.[8]putsforward a CUDA-based design of the MD5 hash algorithm on GPU according to the specific application needs and its implementation, which based on C-language, is comprehensive optimization in terms of the characteristics of GPU and CUDA.[9]was presented an efficient implementation for MD5-RC4 encryption using NVIDIA GPU with a novel CUDA programming framework.The MD5-RC4 encryption algorithm built on NVIDIA GeForce 9800GTX GPU with 580 MHz core clock and 512 MB of GDDR.The performance of his solution was compared with the implementation running on an AMD Sempron Processor LE-1200 CPU.The results show that his GPU-based implementation exhibits a performance gain of about 3-5 times speedup for the MD5-RC4 encryption algorithm.
In software direction;[1]was presented the data integrity checking method based on MD5 to ensure that the data of an information system is in a correct state, his checking system was built as software by C ++ .[10]suggests a software implementation of a digital envelope for a secure e-commerce channel that combined the hashing algorithm of MD5, the symmetric key algorithm of AES and W PDF created with pdfFactory Pro trial version www.pdffactory.comthe asymmetric key algorithm of Hyper elliptic Curve Cryptography (HECC) by use Java.The result illustrates that HECC is the best alternative asymmetric key technique rather than ECC and RSA in the digital envelope hybrid cryptosystem.

MESSAGE DIGESTS (MD)
Message Digest (MD) algorithms, also called as Hash algorithms, which generate a unique message digest for an arbitrary message.Also, it's used widely in cryptographic protocols and Internet communication [3].The core of MD algorithm is a hash function, which compress a string of arbitrary length for a string of fixed length.They provide a unique relationship between the input and the hash value and replace the authenticity of a large amount of information (message) by the authenticity of much smaller hash value (authenticator) [2].
One of the most famous algorithms of MD is the MD5 message digest's algorithm developed by Ronald Rivest [4].The message digests to be generated by MD5 algorithm has the irreversible and non-counterfeit features, so MD5 algorithm is superior in anti-tamper capability.Also, it can be considered as a fingerprint of the message, and it must have the following properties: First -must be easy to compute, Second -it must be very hard to compute the message from the digest and, Third -it must be hard to find another message which has the same message digest as the first one [4].This is the algorithm core, which includes four "rounds" of processing.
The value of k, s, and T[i] from the table (1) [4].
In the end of four rounds, the output is added to the input of the first round A=A+AA; B=B+BB; C=C+CC; D=D+DD … (3) 10.Then, the output are 128-bits will arrange as follows;   From equation ( 1), it's clear there are prime five variables this is A, B, F, T, and X each of them has been 32-bits.Then A have an initial value as showed above and then take its value from equation ( 1), and B also have initial value and take its other value from equation (2).F takes its value from expressions above inside the loop.T has values from Table (1).Then the important variable X also 32-bit and it represents the values from the IM-input massage, and by the loop will process all data.Then the output as in point 10 will be;    and Table (2).   Table (2  We can note the satisfaction of the properties which stated in Message digest's section, where the implementation made for easy computes, and just now nearly PDF created with pdfFactory Pro trial version www.pdffactory.comimpossible to compute the input messages from the digest output.Also, never to find the similarities between the all messages digest. Another point which we can consider as a power point of our implementation, this is the use of the Xilinx IC XC3S1400A -FPGA.Where, in comparison with [3] and [4] the use of this IC represents best selection as in Table (3) which represents the devise utilization.

CONCLUSIONS
Compare with the normal execution using CPU and GPU, the FPGA Xilinx technology represents the best means to achieve the propose of MD5, for several reasons such as low power consumption, low cost, and the important factor to achieve the independence of action.Also, the ability to develop the design while maintaining the components and incorporating an improvement to the low level.Also, the select of the Xilinx IC XC3S1400A compared with other in Xilinx family represent good selection for this purpose.
PDF created with pdfFactory Pro trial version www.pdffactory.com MD5 algorithm flowchart shown in Figure (1) consist of the following steps;1.Check the no. of bits (length) of the original massage (NOM).2. Add No. of bits to the input massage (IM) so total length of the result data equal to the multiple of 512-64(the add bit are 1 0 0 ……….0). 3. Add 64-bit which represent the length of the (IM) to the result of point 2 the final will represent by M. where M (multiple of 512 bits).4. Divided M to blocks (B) each one have 512 bits. 5. Divided (B) to 16 blocks (X) each one have 32-bits.6.The algorithm steps have 4 rounds and each round have 16 steps.Then total steps are 64 steps.7.There are four 32-bit shift registers, each one have initial (Hex.)values as followvalues of A, B, C and D are stored temporary in AA, BB, CC, and DD respectively.9. Then;

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Figure ( 3
Figure (3) represents the waveform output of the VHDL implementation.Sixteen examples for test the implementation and have been taken, nine of them have been recorded as in Figure (3)and Table (2).

‫ﻧﻤﻮذج‬ VHDL ‫ﺧﻮارزﻣﯿﺔ‬ ‫ﻟﺒﻨﺎء‬ MD5
PDF created with pdfFactory Pro trial version www.pdffactory.com Each round consist of 16 steps and each step uses a 64 element table T [0…63] for T[i], i is the index as shown in table 1,the four rounds have similar structure but each uses different functions F, G, H and I.
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