Design and Implementation of Programmable Multi-Mode Digital Modulator for SDR Using FPGA

The design of programmable multi -mode digital modulator for software defined radio (SDR) technology using FPGA is developed and investigated in this paper. The system generator from Xilinx and MATLAB tools are used for FPGA design as well as the implementation of the modulator over a Virtex-4 FPGA board. The HDL language on Xilinx ISE is used to generate the bit stream of the modulator algorithms into ADC/DAC device and FPGA board. The modulated signal obtained from MATLAB simulation is evaluated with the tested signal to verify the system functionality. Lastly, the optimally synthesized netlist of the integrated design is downloaded into Xilinx Virtex-4 FPGA MB development board. The verification of DAC output signal via oscilloscope demonstrate the empirical real-time signals similar to the simulated waveforms. Results shows the successfully implementation steps as timing constraint of FPGA is accepted without error. The proposed design is promising to enhance the current and next generation of communication systems with less power consumption compared with conventional design in term of FPGA Slices and Look Up Tables (LUTs) during the implementation process. The improvement in Slices and LUTs produce by ISE project utilization summary is 65% and 79% respectively.


INTRODUCTION
he current and future wireless communication standards are rapidly changing and growing along with conventional standards.The conventional mobile phone could support only limit number of standards and the modern technology has changed toward the software defined radio (SDR) idea [1].The technology of SDR need reconfigure digital components to performs the necessary digital signal processing (DSP) with transceiver of baseband information in the intermediate frequency (IF).[2].The requirements of mobile handset nowadays is essentially support the implementation of physical layer protocols of many communication mode to provide the user demand at anytime and anywhere within single device [3].The DSP and FPGA are able with signal processing functionality for hardware realization of the communication standards [4].The SDR facilitate the users and industrial to improve their products in order to achieve the user demands [5].Numerous techniques have evolved to design programmable radio of SDR.The concept of parameterization and dynamic reconfiguration in the digital radio system design which can integrate 2G and 3G standards in ordinary stage was earlier introduce by J. Motila at 1991.Several silicon solutions for design the SDR by the most excellent possible hardware selections has been fined out in [6].Low power SDR prototype module and suitable for many mobile air interface was developed by [7].A real time SDR test bed for baseband processor of wireless standards implementation on general purpose processor (GPP) is described in [8].A low cost design has been adopted for baseband processing in SDR design proposed by [9].A new design framework for common baseband processing after exploring the algorithms for 3G and 4G systems has been produced by [10].One of the more important binary modulation techniques which has used only two phases of the carrier at the same frequency is the binary phase shift keying (BPSK) and quadrature amplitude modulation (QAM) [11].This type of modulation could be generated with bandwidth efficiency and symbol error performance.The latest version of ISE (Integrated Software Environments) from Xilinx [12] could be used to generate the BPSK and QAM bit streams to Virtex-4 FPGAs [13] after the HDL code is built by ModeSim [14] and synthesis tool introduced for Simplicity [15].The Virtex-4 FPGA board is a development platform based on a Xilinx products [15].It provides a development kit for embedded applications of digital signal processing (DSP).The web pack ISE software from Xilinx is completely featured front to back FPGA design solution which offers HDL synthesis device fitting and JTAG programming.The BPSK is a simple one dimension modulation scheme which is a phase of carrier sinusoidal signal changes suddenly by 180 or pi radian for every broadcast of modulating binary sequence [16] .The Block diagram of QAM transmitter using FPGA is shown in Figure 1.The input of QAM with one or zero values is mapped to symbol through polar conversion and local oscillator generate carrier sinusoidal signal with specific frequency to be mixed by multiplier to produce QAM modulating signal [17].

Figure (1) Block Diagram of
The proposed modulator could be integrated with standards and with all standard illustrated in Table work with multiple wireless communication standards is engaged under SDR technology [18].The proposed programmable modulator in this paper could performs any scheme of QPSK, BPSK, QAM and any other digital modulator to serve the SDR transceivers.The principle of BPSK modulator, the binary data is converted to binary code format and multiplied by carrier signal (Fc) as illustrated in Figure signal, c(t) represent the carrier signal and s(t) is modulated signal then could be represented as [19]:

Figure (2): Bock diagram of BPSK modulator design
The bit error rate (BER) is decrease exponentially as SNR increase with AWGN channel which produce good signal quality at the receiver side [20].Though, the symbol error rate in BPSK is less compared with other modulator techniques as clearly shown in Equation (3).Then, the BER of BPSK could be represented by mean of average energy per bit ( ) and noise power ( ) as in [21] = In the case of QAM modulation, the variation of the one used for PSK.Hence, the generalized PSK allows changing both amplitude and phase and all points lie in circle.Therefore, the I and Q values are related to each other.So, all value have the same values.If the amplitude changed from symbol to symbol, then the modulation is called quadrature amplitude modulation (QAM).This techniques could considered as linear combination of two DSB-SC signal.Therefore, its AM and PM modulation as shown in Equation ( 4).

I Q
To create the hybrid type of modulation that varies both amplitude and phase, Equation (4) could be used as QAM modulator.For example, if we have 16 symbols represented a four bit word, then this modulation called 16 QAM modulator.

Implementation Design Flow
In this section, the developments explained in detailed.The proposed model could be divided into 2 parts The implementation steps are read in the constraints file that consists of three steps: translate, map, and place & of the synthesis tool into a large single netlist.A netlist in general, is a large which is compressed at this stage to remove any logical symbols in the flattened netlist into physical components, specific to the target device.The place and route step places each of these physical FPGA chip and connects them through the switch matrix and dedicated routi To create the hybrid type of modulation that varies both amplitude and phase, Equation could be used as QAM modulator.For example, if we have 16 symbols represented a four bit word, then this modulation called 16 QAM modulator.
, the developments of configurable baseband QAM modulator is proposed flow chart of design and implementation of QAM be divided into 2 parts specifically software and hardware, as illustrated in The proposed flow shows the simulation and implementation steps by using MATLAB and Xilinx System Generator's blocks.Following the simulation of QAM model in fixed point and verification with SIMULINK model, the next step is the implementation of the model in the FPGA form.To implement the QAM modulator many tools to download the designed model as a bit .The ModelSim blocks are an helper block used to design the Verilog module of integrated design.The ModelSim output is feed back to SIMULINK for implementation steps are read in the constraints file that consists of three main s: translate, map, and place & route.The translate step basically compress the output of the synthesis tool into a large single netlist.A netlist in general, is a large list of gates which is compressed at this stage to remove any pecking order.The map step collect the logical symbols in the flattened netlist into physical components, specific to the target device.The place and route step places each of these physical components onto the FPGA chip and connects them through the switch matrix and dedicated routing lines.The System Generator [22] block is required for Simulink model that contains any block from Xilinx block set and is normally located at the top level.It is used to set Simulink system period: 1 unit, FPGA system clock and sample rate f s = 100 MSps.In addition it is used to generate HDL netlist of QAM with test-bench file written in Verilog codes.Finally, it is convenient to represent the normalized sampling period T s as 1 unit sample time, or 1 latency.The Resource Estimator block is used to compute an estimation of FPGA resources for implementing the QAM enclosed within Xilinx Gateway.

Proposed Simulation and implementation flow
The  After matched-filtering with adjusted gain, the IQ filtered data resemble the IQ baseband modulated signals.Then, the IQ synchronized symbols would be the optimal IQ filtered data samples that have been captured at optimum sampling instant.In order to verify performance of the BPSK system implemented using FPGA via DAC in P240 Analog Module, the sharp-edged recovered bits were intentionally pulse-shaped to become the smoothed bits.However, it can be found that the recovered bits and smoothed bits for QAM are all equivalent.

HDL Design
The configurations of ADC and DAC are set during Serial Programming Interface (SPI).The Verilog HDL module of setup configuration and Verilog HDL netlist of QAM modulator are verified firstly before combining both to become HDL module of integrated design.Both the simulation results in ModelSim environment are shown in Figure 6.Considering the real-time implementation of integrated design of QAM transmitter and setup configuration using FPGA and P240 Analog Module, the ADC and DAC in P240 should be configured first prior to the running of DSP design, in order to avoid instability of ADC and DAC that can produce undesired outputs to or from FPGA during process of configuring ADC and DAC.Consequently, the clock enable (ce) of FPGA design is disabled during the transfer of SPI codes to ADC and DAC in P240.Controlling the main ce would be easier rather than clock enable clear (ce_clr) which requires additional logics to adjust sampling phase of all the multi-sample data when it is asserted.

Figure (6): HDL simulation result of QAM Netlist
Though, the Xilinx ISE group Technology" (XST), but it can only synthesize HDL Generator.Consequently, Synplify HDL module of integrated design in 2 stages of logic compilation technology mapping.Before doing have to be assigned accordingly to user guide integrated design would ignore the pin analog input is involved in BPSK modulator QAM modulated signal.Timing characteristics performance of FPGA implementation.The required path Xilinx FPGA element should be less than the requested (constrained) clock period.timing slack (requested period − estimated period) should be positive integrated design has to be redesigned process and BPSK modulators (i.e.CLK_100 and LIO_CLKIN_1 are set to 100 MHz for both.The positive of design synthesis in Table 2 is meet the timing requirement any Xilinx IP (Intellectual Property) core is used in the integrated design, ther another clock called System after clocks of CLK_100 and

Hardware Implementation
The Development board of Virtex development platform for designing and verifying applications b family.This board enables designers to implement DSP and embedded processor based applications with extreme flexibility using IP cores and customized modules.The Virte 4 FPGA along with Xilinx soft processor core makes it possible to prototype processor based applications, enabling software design teams early access to a hardware platform prior to working with the final product expansion module standard, allowing application specific expansion modules to be easily added.

Part (A), No.7, 2014 Design and Implementation of Programmable
Multi -Mode Digital Modulator for SDR Using FPGA 1663 group has its own synthesis tool "Xilinx Synthesis (XST), but it can only synthesize HDL netlist generated from System , Synplify Pro software is used to execute logic synthesis for the module of integrated design in 2 stages of logic compilation , optimization, and .Before doing the final stage of synthesis, FPGA pins (pad locations) ned accordingly to user guide.Notice that the (3) final synthesis for the integrated design would ignore the pin assignment of ADC_IN and DAC_DB since no is involved in BPSK modulator, and only one DAC analog output is used fo Timing characteristics is an significant matter that affect the performance of FPGA implementation.The required path delay (estimated period) for less than the requested (constrained) clock period.Thus − estimated period) should be positive value; otherwise the redesigned.The clock frequencies used for the ADC/DAC SPI (i.e.CLK_100 and LIO_CLKIN_1 or ADC_CLKOUT) set to 100 MHz for both.The positive slack values in timing report generated by ISE meet the timing requirement of FPGA constraint time.If Property) core is used in the integrated design, there will be another clock called System after clocks of CLK_100 and LIO_CLKIN_1.

: Timing Report of Design Synthesis
Virtex-4 FPGA show in Figure 7 [13] offer a total development platform for designing and verifying applications based on the Xilinx enables designers to implement DSP and embedded processor based applications with extreme flexibility using IP cores and customized modules.The Virte x soft processor core makes it possible to prototype processor based applications, enabling software design teams early access to a hardware platform working with the final product board.The board also supports the P240 sion module standard, allowing application specific expansion modules to be easily

Design and Implementation of Programmable
Synthesis netlist generated from System logic synthesis for the on, and the final stage of synthesis, FPGA pins (pad locations) final synthesis for the since no DAC analog output is used for the delay (estimated period) for Thus, value; otherwise the clock frequencies used for the ADC/DAC SPI ADC_CLKOUT) generated by ISE .If e will be total ased on the Xilinx enables designers to implement DSP and embedded processor based xsoft processor core makes it possible to prototype processor based applications, enabling software design teams early access to a hardware platform P240 sion module standard, allowing application specific expansion modules to be easily   The device utilization for Virtex-4 FPGA after Map process is shown in Figure 10.As shown in the post PAR (final) static timing report in Table 3, the positive worst case slacks (constrained period -best case required period) fulfill the timing requirement.The maximum allowable sampling rate for QAM transmitter used in Virtex-4 FPGA is 206.6543MSps (= 1/4.839ns).However, the maximum sampling rate of LIO_CLKIN_1 from ADS5500 is 125 MSps; thus the maximum sampling rate of QAM transmitter that can be used in Virtex-4 FPGA MB development board with P240 Analog Module is 125 MSps.

Figure (10): Device utilization for Virtex
The DAC Channel A output from P240 Analog Module is connected to oscilloscope in order to display real-time result in analog domain.By observ QAM transmitted signal and simulated signal waveform characteristics of the QAM characteristics such as pulse interval (ns) and lower/higher amplitude peak as shown in Figure 11 and Table 4.The pulse interval of the real interval of the simulated signal is likewise 100 ns.This means that no error difference is found between them.The timing error is satisfied because of accurate timing adjustment, whereas errors of 5% are found between the amplitude of simulated signal because of hardware constraints related to wiring, chip, and printed circuit board (PCB).However, the errors are acceptable.The real simulated results in the time domain show e The DAC Channel A output from P240 Analog Module is connected to oscilloscope in time result in analog domain.By observing the real-time result of and simulated signal as shown in Figure 11.The real-time characteristics of the QAM are compared with simulation waveform characteristics such as pulse interval (ns) and lower/higher amplitude peak as shown in .The pulse interval of the real-time signal is 100 ns and the pulse interval of the simulated signal is likewise 100 ns.This means that no error difference is found between them.The timing error is satisfied because of accurate timing adjustment, whereas errors of 5% are found between the amplitude of real-time signal and the amplitude of simulated signal because of hardware constraints related to wiring, chip, and .However, the errors are acceptable.The real-time and in the time domain show equivalence in shape.

Design and Implementation of Programmable
The DAC Channel A output from P240 Analog Module is connected to oscilloscope in time result of time are compared with simulation waveform characteristics such as pulse interval (ns) and lower/higher amplitude peak as shown in signal is 100 ns and the pulse interval of the simulated signal is likewise 100 ns.This means that no error difference is found between them.The timing error is satisfied because of accurate timing adjustment, time signal and the amplitude of simulated signal because of hardware constraints related to wiring, chip, and and

Results Evaluation
Comparing with conventional design, the proposed reconfigure digital modulator look better performance and less FPGA area resulting in low power resulting FPGA implementation in terms of Slices and LUTs is illustrated in Table 5. Comparing with conventional design, the proposed reconfigure digital modulator look better performance and less FPGA area resulting in low power consumption .The resulting FPGA implementation in terms of Slices and LUTs is illustrated in Table 5. Comparing with conventional design, the proposed reconfigure digital modulator look .The

Figure ( 3 )
. The proposed flow shows the simulation and implementation steps MATLAB and Xilinx System Generator's blocks.model in fixed point and verification with SIMULINK model, the next step is the implementation of the model in the model in FPGA, Xilinx presents stream to FPGA.The ModelSim blocks are an module of integrated design.The ModelSim output is verification.

Figure
Figure (4) DSP Model of input ports of the top level QAM model are Xilinx Gateway in blocks ( reset and select ) is sampled at T s of 16 units sample time to form Boolean output to the inputs rst of the PR Bit Generator and Symbol Mapper subsystems.The IQ symbols and IQ baseband modulated signals are grouped in pairs by Real-Imag to Complex1 and 2 blocks respectively for better wiring illustration.The fixed point principles of the inputs are transformed to floating point double precision values by Xilinx Gateway Out blocks to form symbol integer output.The simulation results of top level QAM displayed in the Scope block are illustrated in Figure 5.For noiseless low-pass equivalent channel, the IQ input signals received by the BPSK are identical to the IQ baseband modulated signals.

logic 1 Part (A), No.7, 2014 Design and Implementation of Programmable Multi -Mode Digital Modulator for SDR Using FPGA 1657 Block Diagram of QAM Modulator The
(1)posed modulator could be integrated with QAM modulator communication illustrated in Table(1).The capability of single device to work with multiple wireless communication standards is engaged under SDRThe proposed programmable modulator in this paper could performs any QAM and any other digital modulator to serve the SDR

Design and Implementation of Programmable communication . The capability of single device to work with multiple wireless communication standards is engaged under
SDRThe proposed programmable modulator in this paper could performs any QAM and any other digital modulator to serve the SDRThe principle of BPSK modulator, the binary data is converted to binary code format and .If m(t) is bipolar format the BPSK signal and