Dynamic Power Consumption In CMOS N Bit Full-Adder Circuit

Authors

• Amal Hasan, Control and Systems Engineering Department, University of Technology - Iraq
• Qusay Al-Doori, Control and Systems Eng., University of Technology - IraqFollow

Keywords

CMOS, Dynamic power, Full adder

Document Type

Research Paper

Abstract

This paper discusses power consumption in the full adder circuit using some fabrication technologies. Though many studies related to power consumption in the full adder circuit were performed, however, few investigations about the effect of the number of bits on the power consumption are addressed. In this paper, the effect of changing the number of bits on the power consumption and time delay of the full adder circuit will be observed and the effect of changing the technology size is going to be calculated. The results will show that there is a direct relationship between the number of bits and power.

Recommended Citation

Hasan, Amal and Al-Doori, Qusay () "Dynamic Power Consumption In CMOS N Bit Full-Adder Circuit," Engineering and Technology Journal: Vol. 39: Iss. 5, Article 7.
DOI: https://doi.org/10.30684/etj.v39i5A.1846

DOI

10.30684/etj.v39i5A.1846

First Page

754

Last Page

767